SCU-RTL Benchmarks

October 1998

This suite of RTL benchmarks comprise a mix circuits such as controllers, DSP cores and ALU. All circuits are described in Verilog HDL. They were simulated with Cadence Verilog. Synopsys tools were used for synthesis. The circuits are characterized as shown in the table below. To access, select the appropriate title. Each circuit is accompanied with its testbench. You may also download the benchmarks form: ftp.engr.scu.edu and switching to subdirectory pub/smourad/scu-rtl-bench.
 

Name
Assoc. Circuit
Code Lines
Inputs
Outputs
Gates
1 IIR, IIR-tb   189 27 9 15790
2 FIR, FIR-tb   255 10 10 2264
3 IDCT, IDCT-tb RAM 435 41 99 17341
4 USBus interface, USB-tb Host 996 13 35 1158
5 sdram-cntl ---- sdram-tb RAM  1523 62  67  3654 
6
MMX, MMX-tb,
main.mem, mmx.mem 
461
20
42
3031
7
Firewire, Fire-tb
 
 931
10 
165 
 2865
8
Router (Packet), Router-tb
RAM 
 483
33
 66
3031 
9
Booth multiplier tbooth.html
 
 237
10
16
819
10
ALU, ALU-tb
 
51
41
 17
975
11
DSP-core-System
RAM
 1293
 
 
 
12
Flat-DSP-Core

Flat-DSP-Core-tb

RAM
1068
 
 
 
 
* For the purpose of simulation, if necessary We have used the circuits to test algorithms for partial scan design and core-based testing. You may use some or all of them and we would appreciate your referencing to them in your publication as "SCU-RTL", Santa Clara University, Santa Clara, CA 95053.

For questions, please send email to smourad@scu.edu

Acknowledgement: I would like to thank Dr. Yacoub M. ElZiq of Synopsys who has been the motivator for the posting of this suite of benchmarks, Nivetita Gouda of Sun Microsystems for the development and validation of the benchmarks, and also to the graduate students, Shabnam Sikandar and Aliya Shafquat for their contributions.