| Chapter | Last Updated | 8. Design for Test | 08/18/01 |
| 1. An Overview | 08/18/01 | 9. Scanpath Design | 08/18/01 |
| 2. Defects,Fail.,&Fault | 08/18/01 | 9e.Scanpath Design | 08/18/01 |
| 3. Data Representation | 08/18/01 | 10.Boundary Scan | 09/25/01 |
| 4. Design Cycle | 08/18/01 | 11. BIST | 08/18/01 |
| 5. The Role of Simul. | 08/18/01 | 12. Memory Testing | 08/18/01 |
| 6. Test Pattern Gen. | 08/18/01 | 13. FPGAs &Micropro. | 08/18/01 |
| 6s. Sequential TPG | 08/18/01 | 14. Test Synthesis | 08/18/01 |
| 7.. IDDQ Testing | 08/18/01 | 15. SOCs | 08/18/01 |