Research Area: My research is in the area of Design for Test, and testability at RTL levels. Developing testability modeling rules for RTL design using C/C++. These rules enables one to have better design when writing C hardware descriptions, and helps synthesis tools achieve high fault coverage.
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Engineering and Management positions: ESS Technology, Compass Design Automation (Subsidiary of VLSI Technology), and National Semiconductor before joining Cisco Systems in 1998. EMail: dkay@cisco.com.
Research Area:
Areas of Interest: ASIC/VLSI Design and Test Technology - Interactive Built-In Self-Test, Boundary Scan Test Technology (IEEE 1149.1 and IEEE P1532), Remote on-line Testing via Network. Embedded core based design and test (IEEE P1500). Computer Aided Test Synthesis and Verification. Java and XML programming Technology. Design Reuse and IP testability for System on a Chip (SoC). He is a voting member of IEEE P1500 (Standard for Embedded Core Test)
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bEST Inc. Her primary duty is developing and teaching workshops to train hardware and software engineers in the use of the Intel IXP1200 and Analog Devices' SHARC DSPs. Prior to joining bEST, Mary Sue was a DSP Field Applications Engineer with Analog Devices. She has board level and real-time firmware design experience from working at Anritsu and Onstream Networks (now part of 3Com). She also has IC design experience from consulting work to reduce ground bounce at Philips Semiconductor.
She holds a M.Eng. from UC. Berkeley in communications theory and a B.E.E. (magna cum laude) from Villanova University.
marysue.haydt@analog.com.
Research Area:
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Technological University, Mendoza, Argentina, in 1978, the M.S. degree in
Electrical Engineering from Santa Clara University, Santa Clara, California,
in 1994, where he is currently working toward the Ph.D. degree in Electrical
Engineering. From June 1978 to June 1989 he was with INVAP, Argentina, where he worked at the Electronics Division of the Bariloche Atomic Center and was involved in Solid State and High Energy Physics, designing instrumentation for research in in those areas and Neutronics. Then moved into Nuclear plants instrumentation & control. Worked at KWU-Siemens (1983-1984) Erlangen, Germany for Atucha II project. Designed microprocessor based industrial controllers. Designed embeded microprocessor (joint venture INVAP & International Microelectronic Products,(IMP) San Jose, Ca 1986-1987. He was at Cadence Design Systems, San Jose, Ca. from july 1989 to Jan. 1993, managing a CAE Group. He joined Analog Devices Inc. Santa Clara, Ca. from Feb. 1993 to April 1997, at the New Products Div, working in Circuit design layout and
verification of analog and mixed signal devices. From April 1997 to March 1998
he was with Rambus Inc. Mountain View, Ca., working on design of high speed interfaces.
In March 1998 he joined Sun Microsystems, Sunnyvale, Ca. - Microelectronics,
where he is currently working on the next generation of microprocessors for the SPARC
III/IV series. Email: miguel.litvin@eng.sun.com.
Research Area His research interests include high performance digital design, wave pipelining, dynamic logic families as self reset logic, processor architec-ture and testing.
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He is presently working on his Ph.D. degree at Santa Clara University, in Santa Clara,
California, under Professor Samiha Mourad. His present research interest is in testability
enhancements of mixed signal IC's. Email:san_imi@pacbell.net
Research Area: As advanced circuit technologies, such as Fast Ethernet, 56 Kbps modems, and ADSL, are reaching maturity, and even more advanced technologies, such as GigabitEthernet and USB 2.0, 1394b, are emerging, digital communication circuits are poised for the future. My research is on testability enhancements, namely Design-for-Test (DFT) techniques and Built-in-Self-Test (BIST) techniques, implementable in mixed signal circuits used in advanced digital communication circuits.
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He has been working in the testing industry for 5 years. He holds a BSEE ('88)
degree and an MSEE ('92) degree from Santa Clara University tegan@mtest.teradyne.com
Research Area: The main focus of his work is on testing Phase Locked Loops (PLLs) which are embedded in digital circuitry (e.g. in an FPGA or System-On-Chip). This area has been somewhat neglected because of the difficulty of observing the PLL under those conditions. Having developed a series of tests to characterize the PLL, he is currently concentrating on improving their effectiveness. Future work will include the application of these methods to Design For Test and BIST solutions to the problem of testing the PLL in these restricted conditions.
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Research Area: Zemo’s research interest is signal integrity analysis, more specifically crosstalk analysis. Also, Modeling and signal integrity analysis of on-chip and off-chip interconnections.
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