This section is the roadmap for the book. From the onset, it relates design and testing for the purpose of obtaining reliable electronic products. Chapter one is an introduction that explains the objectives of the book and distinguishes design verification from testing. While design verification checks the compliance of the design to specifications, the intent of testing is to show that the design is error free. This chapter also briefly describes the preparation needed to actually test the final product and the processes and the tools used in this preparation ñ test pattern generation and design to facilitate testability of the product.

Before embarking on detailing the topics presented in Chapter One, it is important to know the causes of product failures. Chapter Two gives a thorough description of the possible defects that are encountered in electronic products and explains the need for mapping the defects to faults on the structural and behavioral levels of the design. Most failures of an electronic product are due to manufacturing defects, but they may also be due to noise induced by the operation of the product. Since the overwhelming majority of VLSI systems utilize CMOS, the emphasis will be on MOS technology.

Preparation for testing the product starts from its inception as a design idea. It is thus very important to learn how the design is represented at different stages of its life cycle. Towards this end, Chapter Three presents taxonomy of design that is used to explain the different activities of the design cycle in Chapter Four. The automated design processes are known as synthesis and they follow algorithms that mostly operate on graphs.

The knowledge gained in this part has a two-fold benefit. First, it will facilitate the understanding of the following parts of the book. Second, it will mold a mind set on why design and test can no longer be independent topics.

An Overview Of Testing.

1.1 Reliability and Testing
1.2. The Design Process
1.3 Verification
1.3.1 Functional Simulation
1.3.2 Timing Simulation
1.4 Testing
1.5 Faults and their Detection
1.6 Test Pattern Generation
1.7 Fault Coverage
1.8 Types of Tests
1.8.1 Exhaustive Tests
1.8.2 Pseudo-exhaustive Tests
1.8.3 Pseudo-random Tests
1.8.4 Deterministic Tests
1.9 Test Application
1.9.1 On-Line versus Off-Line Tests
1.9.2 Automatic Test Equipment (ATE)
1.9.3 On-chip versus Off-chip Testing
1.10 Design for Test
1.10.1 Controllability
1.10.2 Observability
1.11 Testing Economics
1.11.1 Yield and Defect Level
1.11.2 Fault Coverage and Defect Level
1.12 To Explore Further
1.13 References
1.14 Problems

Defects, Failures, And Faults.

2.1 Introduction
2.2 Physical Defects

2.2.1 Extra and Missing Material
2.2.2 Oxide Breakdown
2.2.3 Electromigration

2.3 Failures Modes

2.3.1 Opens
2.3.2 Shorts

2.4 Faults
2.5 Stuck-at Faults

2.5.1 Single Stuck-at Faults
2.5.2 Multiple Stuck-at Faults

2.6 Fault Lists

2.6.1 Equivalence Relation
2.6.2 Dominance Relation
2.6.3 Fault Collapsing

2.7 Bridging Faults
2.8 Shorts and Opens Faults

2.8.1 NMOS Circuits
CMOS Circuits

2.9 Delay Faults
2.10 Temporary Failures

Transient Faults
Power Supply
Metastability
Radiation Induced Failures
2.10.2 Intermittent Faults

2.11 Noise Failures
2.12 References
2.13 Problems

Design Representation.

3.1 Levels of Abstraction
3.2 Mathematical Equations

3.2.1 Switching Functions
3.2.2 Boolean Difference
3.2.3 Finite State Machines
3.2.4 Transistor Level Representation

3.3 Tabular Format

3.3.1 Truth tables
3.3.2 State tables

3.4 Graphical Representation
3.5 Graphs
3.6. Binary Decision Diagrams (BDDs)
3.7 Netlists
3.8 Hardware Description Languages

3.8.1 The Verilog HDL
3.8.2 The VHDL Language

3.9 References
3.10 Problems

Vlsi Design Flow.

4.1 Introduction
4.2 CAD Tools
4.3 Algorithms
4.4 Synthesis

4.4.1 Behavioral Synthesis
4.4.2 Logic Synthesis

4.5 Design Methodologies
4.6 Semi-Custom Design

4.6.1 Standard Cell Design
4.6.2 Mask-Programmable Gate-arrays (MPGA)
4.6.3 Programmable Devices

4.7 Physical Design

4.7.1 Floor planning
4.7.2 Placement
4.7.3 Routing
4.7.4 Backannotation

4.8 References
4.9 Problems

Test Flow

Simulation plays an indispensable role in electronic product design and testing. It is still the main vehicle for design verification although many efforts are presently made to use formal verification techniques in CAD tools. In addition, fault simulation helps in assessing the quality of the test pattern generated to test the products. Simulation is the topic of Chapter Five where we will show how it evolved to facilitate the verification of todayís very dense and large circuits.

Chapter Six, addresses automatic test pattern generation (ATPG) and covers mostly what is known as deterministic test pattern generation. In the past, test pattern generation was relying on fault detection by measuring the voltage signal at the circuit outputs. Nowadays, in addition to voltage measurement, current measurements are also used. This approach, which is known as IDDQ testing, is possible only for CMOS circuits that comprise most of present day electronic circuits. Chapter Seven presents current testing which is very effective at uncovering many defects that voltage testing cannot detect. A new paradigm of defect detection is becoming very relevant and coexists with the traditional fault coverage of that used in current testing. Moreover, current testing is facilitating defect diagnosis.

Role Of Simulation In Testing.

5.1 Introduction
5.2 Simulation of Large Designs

5.2.1 Testbenches
5.2.2 Cycle-based Simulation

5.3 Logic Simulation
5.4 Approaches to Simulation

5.4.1 Compiled Simulation
5.4.2 Event Driven Simulation

5.5 Timing Models

5.5.1 Static Timing Analysis
5.5.2 Mixed Level Simulation

5.6 Fault Simulation

5.6.1 Parallel Fault Simulation
5.6.2 Deductive Simulation
5.6.3 Concurrent Fault Simulation

5.7 Fault Simulation Results

5.7.1 Fault Coverage
5.7.2 Fault Dictionnary

5.8 References
5.9 Problems

Automatic Test Pattern Generation.

6.1 Introduction
6.2 Terminology and Notations

6.2.1 Basic Operations
6.2.2 Logic and Set Operations
6.2.3 Fault List

6.3 The D-Algorithm

6.3.1 The Case of an Internal Node
6.3.2 The Case of a Primary Input
6.3.3 The Case of a Primary Output
6.3.4 Alternative Strategies

6.4 Critical Path
6.5 Backtracking and Reconverging Fanout
6.6 PODEM
6.7 Other Algorithms

6.7.1 FAN Algorithm
6.7.2 Socrates

6.8 Testing Sequential Circuits

Functional Testing
6.8.2 Deterministic Test Pattern Generation

6.9 References
6.10 Problems

Current Testing.

7.1 Introduction
7.2 The Basic Concept
7.3 Fault-Free Current

7.3.1 Switching and Quiescent Currents
7.3.2 Switching Delays

7.4 Current Sensing Techniques

7.4.1 Off-Chip Measurement
7.4.2 On-Chip Measurement

7.5 Fault Detection

7.5.1 Leakage Faults
7.5.2 Bridging Faults
7.5.3 Stuck-Open Faults
7.5.4 Delay Faults

7.6 Test pattern Generation

7.6.1 Switch Level Model-Based
7.6.2 Leakage Fault Model-Based

7.7 Deep Submicron Technology
7.8 References
7.9 Problems

Design For Test

The knowledge presented in the first seven chapters paves the way to designs that facilitates testing, Design for Testability. This part of the book consists of four chapters.

Chapter Eight outlines mere ìcommon senseî approach, adhoc DFT techniques. However simple they may be, these ad hok techniques can be very powerful. For example, a divide and conquer approach may make quiet a difference in testing the product. The next three chapters cover structured techniques.

Chapter Nine helps reduce the complexity of, mainly synchronous, sequential circuits. It is very widely used and becoming a standard feature in electronic circuits. It has been practiced on asynchronous circuit too.

Chapter Ten is on Boundary- Scan. This technique was initially thought for Printed Circuit Boards (PCB), but it is becoming very useful for ICs too. This DFT technique follows a standard, IEEE Standard 1149.1 and is used, also for debugging and diagnosis.

Built-In Self-Test is the topic of the last chapter in Part III. At the beginning, BIST was applied to random logic, but subsequently it has been used for memory testing, RAMBIST, microprocessors, and FPGAs. After explaining its principles, its use in conjunction with scan design is also described.

Ad Hoc Test Techniques.

8.1 Introduction
8.2 The Case for DFT

8.2.1 Test Generation and Application
8.2.2 Characteristics of Present VLSI

8.3 Testability Analysis
8.4 Ad Hoc Techniques

8.4.1 Initialization
8.4.2 Observation Points
8.4.3 Control Points

8.5 Partitioning for Testability
8.6 Easily Testable Circuits

8.6.1 C-Testability
8.6.2 Scalable Testing

8.7 References
8.8 Problems

Scan-Path Design.

9.1 Introduction
9.2 Scan-Path Design
9.3 Test Pattern Generation
9.4 Test Pattern Application

9.4.1 Testing the Flip-flops
9.4.2 Testing the Combinational Part of the Circuit

9.5 Example for Scan Path Testing
9.6 Storage Devices

9.6.1 Two Port Flip-flop
9.6.2 Clocked Latch

9.7 Scan Architectures

9.7.1 Level-Sensitive Scan Design (LSSD)
9.7.2 Scan-Set Architecture

9.8 Multiple Scan Chains
9.9 The Cost of Scan-Path

9.9.1 Extra Area and Pins
9.9.2 Performance
9.9.3 Test Application Time
9.9.4 Heat Dissipation

9.10 Partial Scan Testing

9.10.1 Definition
9.10.2 Selecting Scan Flip-flops
9.10.3 Test Application

9.11 Ordering Scan Chain Flip-flops

9.11.1 Optimizing for Test Application
9.11.2 Optimizing Interconnect Wiring

9.12 References
9.13 Problems

Boundary-Scan Testing.

10.1 Introduction
10.2 Traditional Board Testing
10.3 The Boundary-Scan Architecture
10.4 The Test Access Port
10.5 The Registers

10.5.1 The Boundary-Scan Cell (BSC)
10.5.2 Bypass Register
10.5.3 Boundary-Scan Register (BSR)
10.5.5 The Device Identification Register

10.6 TAP Controller

10.6.1 The Controllerís States
10.6.2 The Instruction Set

10.7 Modes of Operations

10.7.1 Normal Operation
10.7.2 Test Mode Operation
10.7.3 Testing the Boundary-Scan Registers

10.8 Boundary-Scan Languages

Cost of Boundary-Scan
To Explore Further
References
Problems

Built-In Self-Test.

11.1 Introduction
11.2 Pseudo-Random Test Pattern Generation

11.2.1 Linear Feedback Shift Register
11.2.2 LFSR Configurations
11.2.3 Mathematical Foundation of LFSR

11.3 Response Compaction

11.3.1 Parity Testing
11.3.2 One Counting
11.3.3 Transition Count
11.3.4 Signature Analysis
11.3.5 Space Compaction

11.4 Random Pattern Resistant Faults
11.5 BIST Architectures

11.5.1 Built-In Self-Testing
11.5.2 Autonomous Test
11.5.3 Circular BIST
11.5.4 BILBO
11.5.5 Random Test Socket
11.5.6 STUMPS

11.6 References
11.7 Problems

Special Structures

The fourth Part comprises of two chapters and investigates how testing is performed or applied to specific structures. Each of the three structures, RAMs, FPGAs, and microprocessors, makes use of functional fault model since the use of structural fault models would make their testing untraceable. Testing based on the functional model also detects failures on the associate circuitry decoding logic and the attached registers.

Memory arrays have regular structures but are very dense which causes a whole set of problems in their testing. These problems are compounded when the RAM is embedded in logic chip or in an SOC.

FPGAs come in different varieties but the main interest here is in RAM-based devices. They also have regular array structures but they are much less dense than RAMs Their regular structure is exploited to make them C-testable.

Microprocessors are one of the most used designs but their testability is not sufficiently explored. There are only few models used for testing microprocessors. Most embedded testability constructs such as scan path and BIST are widely used in microprocessors testing.

Memory Test.

12.1 Motivation
12.2 Memory Models

12.2.1 Functional Model
12.2.2 The Memory Cell
12.3.2 RAM Organization

12.3 Defects and Fault Models

12.3.1 Defects
12.3.2 Array Fault Models
12.3.3 Surrounding Logic

12.4 Types of Memory Testing

12.4.1 Specification Testing
12.4.2 Characterization Testing
12.4.3 Functional Testing
12.4.4 Current Testing

12.5 Functional Testing Schemes

12.5.1 MSCAN
12.5.2 The GALPAT Algorithm
12.5.3 Algorithmic Test Sequence (ATS)
12.5.4 Marching Pattern Sequences
12.5.5 Checkerboard Test

12.6 Memory BIST
12.7 Memory Diagnosis and Repairs
12.8 References
12.9 Problems

Testing Fpgas And Microprocessors.

13.1 Introduction
13.2 Field Programmable Gate Arrays

13.2.1 Architecture
13.2.2 Programmability

13.3 Testability of FPGAs

13.3.1 Defects and Faults
13.3.2 Approaches to Testing FPGAs

13.4 Testing RAM-based FPGAs

13.4.1 Functional Testing
13.4.2 IDDQ Testing
13.4.3 BIST
13.4.4 Diagnosis Testing

13.5 Microprocessors

13.5.1 Microprocessor Models
13.5.2 Microprocessor Validation

13.6 Testing Microprocessors

13.6.1 Instruction Set Verification
13.6.2 Testing the Datapath

13.7 DFT Features in Modern Microprocessors

13.7.1 Testing Sun Microsystems Processors
13.7.2 Testing Digitalís Alpha 21164
13.7.3 Testing the Intel Pentium Pro
13.7.4 Testing AMDís K6
13.7.5 Testing IBM S/390
13.7.6 Testing Hewlett Packardís PA8500

13.8 References
Problems

Advanced Topics

Synthesis For Test.

14.1 Introduction
14.2 Testability Concerns
14.3 Synthesis Revisited
14.4 High Level Synthesis

14.4.1 Model Compilation
14.4.2 Transformations
14.4.3 Scheduling
14.4..4 Allocation and Binding

14.5 Test Synthesis Methodologies

14.5.1 Partitioning
14.5.2 Controllability and Observability
14.5.3 Feedback Loops
14.5.4 Scan Path
14.5.5 BIST Insertion

14.6 References
14.7 Problems

Testing Socs.

15.2 Classification of Cores
15.3 Design and Test Flow
15.4 Core Test Requirements
15.5 Conceptional Test Architecture

15.5.1 Sink and Source of Test Data
15.5.2 Test Access Mechanism

15.6 Testing Strategies

15.6.1 Direct Access Test Scheme (DATS)
15.6.2 Use of Boundary-Scan
15.6.3 Use of Scan-Path

15.7 To Explore Further

15.7.1 Virtual Socket Interface VSI Alliance
15.7.2 IEEE P1500 Standard

15.8 References
15.9 Problems

Appendices.

Acronyms and Abbreviation
Bibliography and Standards

Index.