`define SETUP 8'h2D

`define IN 8'h69

`define OUT 8'hE1

 

module main_test;

 

reg reset ;

reg clk;

wire D, D_ ;

 

// RX OUTPUTS

reg [6:0] addr ;

reg [3:0] ep ;

wire [7:0] pid_latch,crc16_latch1,crc16_latch2,data_latch;

wire [3:0] endp_latch ;

wire [6:0] addr_latch ;

 

// TX INPUTS

reg load ;

reg send_eop ;

reg En ;

reg [7:0] DATA ;

 

 

main M1(.reset (reset),

.D(D),

.D_(D_),

.clk(clk),

 

// RX OUTPUTS

.addr_latch(addr_latch),

.endp_latch(endp_latch),

.pid_latch(pid_latch),

.crc16_latch1(crc16_latch1),

.crc16_latch2(crc16_latch2),

.data_latch(data_latch),

 

// TX INPUTS

.TX_EN (En),

.TX_DATA (DATA ),

.TX_LOAD (load),

.send_eop (send_eop)

);

 

//FULL SPEED

pullup (D );

pulldown (D_ ) ;

host M2 (.D(D), .D_(D_), .clk(clk) );

 

initial

begin

load = 1'b0 ;

En = 1'b0 ;

reset = 1 ;

send_eop = 1'b0 ;

clk = 'b0;

forever #100 clk = ~clk;

end

initial

begin

#80

reset = 0 ;

#200

reset = 1 ;

//tests

#2000

addr = 8'h04 ;

ep = 4'h1 ;

M2.send_token (`SETUP, addr, ep) ;

#2000

addr = 8'hFF ;

ep = 4'h3 ;

M2.send_token (`IN, addr, ep) ;

 

 

 

#2000

$display ("Testing TX SIDE ");

// SENDING SYNC, PID(DATA0=C3), DATA=57, DATA=FF, CRC1, CRC2, EOP

load = 1'b0 ;

#100

 

$display (" SENDING SYNC ");

@(posedge clk)

#2 load = 1'b1 ;

DATA = 8'h80 ; //sync

@(posedge clk) ;

#2 load = 1'b0 ;

@(posedge clk);

En = 1'b1 ;

$display (" SENDING DATA PID ");

repeat (6) @(posedge clk);

#1 load = 1'b1 ;

DATA = 8'hc3 ; // DATA0 pid

@(posedge clk);

#1 ; load = 1'b0 ;

$display (" SENDING DATA ");

repeat (8) @(posedge clk);

#1 load = 1'b1 ;

DATA = 8'h57 ; // DATA

@(posedge clk);

#1 ; load = 1'b0 ;

 

$display (" SENDING DATA WITH BIT STUFFING");

repeat (8) @(posedge clk);

#1 load = 1'b1 ;

DATA = 8'hFF ; // DATA, FOR BIT STUFFING

@(posedge clk);

#1 ; load = 1'b0 ;

 

$display (" SENDING CRC 1 ");

repeat (8) @(posedge clk);

#1 load = 1'b1 ;

DATA = 8'h81 ; // CRC1

@(posedge clk);

#1 ; load = 1'b0 ;

 

$display (" SENDING CRC 2 ");

repeat (8) @(posedge clk);

#1 load = 1'b1 ;

DATA = 8'h41 ; // CRC2

@(posedge clk);

#1 ; load = 1'b0 ;

 

$display (" SENDING EOP ");

repeat (8) @(posedge clk);

#1 send_eop = 1'b1 ; // SEND EOP

repeat (2) @(posedge clk);

#1 send_eop = 1'b0 ;

 

En = 1'b0 ;

 

end

 

 

initial begin

$shm_open("waves.shm");

$shm_probe ("M1.*", M1, "M1.RX_STATE.*", "*", clk, addr, ep, D, D_);

end

 

endmodule