module processor_outputs;

 

reg clk;

reg reset;

reg CS;

reg RD;

reg WR;

reg del_WR;

reg [24:0] ADDR;

wire [31:0] temp_data;

wire RAS_L;

wire CAS_L;

wire WE_L;

wire CSA_L;

wire CSB_L;

wire CSC_L;

wire CSD_L;

wire CKE;

wire BS;

wire ready;

wire [10:0] address_to_dram;

wire [31:0] data_to_dram;

wire [31:0] DATA;

reg [31:0] DATA_temp;

 

integer i;

integer j;

integer k,l;

 

parameter mode_reg1 = 11'b00000010000;//burst length = 1 and BS=0 and CAS latency = 1

//parameter mode_reg3 = 11'b00000100000;//burst length = 1 and BS=0 and CAS latency = 2

parameter mode_reg3 = 11'b00000110000;//burst length = 1 and BS=0 and CAS latency = 3

 

//**parameter mode_reg3 = 11'b00000010001;//burst length = 2 and BS=0 and CAS latency = 1

//**parameter mode_reg3 = 11'b00000100001;//burst length = 2 and BS=0 and CAS latency = 2

//**parameter mode_reg3 = 11'b00000110001;//burst length = 2 and BS=0 and CAS latency = 3

 

//**parameter mode_reg3 = 11'b00000010010;//burst length = 4 and BS=1 and CAS latency = 1

//**parameter mode_reg3 = 11'b00000100010;//burst length = 4 and BS=1 and CAS latency = 2

//**parameter mode_reg3 = 11'b00000110010;//burst length = 4 and BS=1 and CAS latency = 3

 

//**parameter mode_reg3 = 11'b00000010011;//burst length = 8 and BS=1 and CAS latency = 1

//**parameter mode_reg3 = 11'b00000100011;//burst length = 8 and BS=1 and CAS latency = 2

//**parameter mode_reg3 = 11'b00000110011;//burst length = 8 and BS=1 and CAS latency = 3

 

//**parameter mode_reg3 = 11'b00000010111;//burst length full = 6 and BS=1 and CAS latency = 1

//**parameter mode_reg3 = 11'b00000100111;//burst length full = 6 and BS=1 and CAS latency = 2

//**parameter mode_reg3 = 11'b00000110111;//burst length full = 6 and BS=1 and CAS latency = 3

 

parameter DATA_store = 32'h1234_5678;

parameter ADDR_store = 25'h018_56A1;

 

parameter burst_length = 1;

//**parameter burst_length = 2;

//**parameter burst_length = 4;

//**parameter burst_length = 8;

//**parameter burst_length = 6; //full

 

read_write contr(.clk(clk), .reset(reset), .WR(WR),

.RD(RD), .CS(CS), .ADDR(ADDR),

.DATA(DATA), .RAS_L(RAS_L), .CAS_L(CAS_L),

.WE_L(WE_L), . CKE(CKE), .BS(BS), .CSA_L(CSA_L),

.CSB_L(CSB_L), .CSC_L(CSC_L), .CSD_L(CSD_L),

.ready(ready), .address_to_dram(address_to_dram),

.data_to_dram(data_to_dram));

dram dram (.clk(clk),

.addr(address_to_dram),

.data_to_dram(data_to_dram),

.BS(BS),

.RAS_L(RAS_L),

.CAS_L(CAS_L),

.WE_L(WE_L),

.CKE(CKE),

.CSA_L(CSA_L),

.CSB_L(CSB_L),

.CSC_L(CSC_L),

.CSD_L(CSD_L));

 

initial

begin

clk=1'b0;

forever #5 clk=~clk;

end

 

initial

begin

#0 reset = 1'b1;

#5 reset = 1'b0;

#20 reset = 1'b1;

end

 

initial

begin

// first operation is write

#0 CS = 1'b1;

@(posedge reset);

@(posedge clk);

@(posedge clk);

CS = 1'b0;

repeat (4) @(posedge clk);

CS = 1'b1;

// second operation is read

@(posedge ready);

repeat (9) @(posedge clk);

CS = 1'b0;

repeat (4) @(posedge clk);

CS = 1'b1;

// third operation is 4 writes

@(posedge ready);

for (l=0;l<burst_length;l=l+1) begin

repeat (9) @(posedge clk);

CS = 1'b0;

repeat (4) @(posedge clk);

CS = 1'b1;

@(posedge ready);

end

// fourth operation is read after 4 writes

repeat (9) @(posedge clk);

CS = 1'b0;

repeat (4) @(posedge clk);

CS = 1'b1;

//opcode operations

@(negedge ready);

repeat(5) @(posedge clk);

CS = 1'b0;

@(posedge clk);

CS = 1'b1;

repeat (6) @(posedge clk);

CS = 1'b0;

@(posedge clk);

CS = 1'b1;

@(negedge ready);

CS = 1'b0;

@(posedge clk);

CS = 1'b1;

repeat (4) @(posedge clk);

CS = 1'b0;

@(posedge clk);

CS = 1'b1;

@(negedge ready);

CS = 1'b0;

@(posedge clk);

CS = 1'b1;

@(negedge ready);

CS = 1'b0;

@(posedge clk);

CS = 1'b1;

end

initial

begin

#0 WR = 1'b1;

@(posedge reset);

@(posedge clk);

@(posedge clk);

WR = 1'b0;

repeat (4) @(posedge clk);

WR = 1'b1;

@(posedge ready);

@(posedge ready);

repeat (9) @(posedge clk);

for (i=0;i<burst_length;i=i+1) begin

WR = 1'b0;

repeat (4) @(posedge clk);

WR = 1'b1;

@(posedge ready);

repeat (9) @(posedge clk);

end

end

initial

begin

// the first write operation

#0 DATA_temp = 32'hZZZZ_ZZZZ;

@(posedge reset);

@(posedge clk);

@(posedge clk);

DATA_temp = {21'h0,mode_reg1};

repeat (1) @(posedge clk);

DATA_temp = 32'hFFEE_FFEE;

repeat (3) @(posedge clk);

DATA_temp = 32'hZZZZ_ZZZZ;

// the second read operation

@(posedge ready);

repeat (9) @(posedge clk);

DATA_temp = {21'h0,mode_reg1};

@(posedge clk);

DATA_temp = 32'hZZZZ_ZZZZ;

// The third operation is four writes

@(posedge ready);

for (j=0;j<burst_length;j=j+1) begin

repeat (9) @(posedge clk);

DATA_temp = {21'h0,mode_reg3};

repeat (1) @(posedge clk);

DATA_temp = DATA_store;

repeat (3) @(posedge clk);

DATA_temp = 32'hZZZZ_ZZZZ;

@(posedge ready);

DATA_store = DATA_store + 1;

end

// the fourth operation is burst read after writes

repeat (9) @(posedge clk);

DATA_temp = {21'h0,mode_reg3};

@(posedge clk);

DATA_temp = 32'hZZZZ_ZZZZ;

end

assign DATA[31:0] = DATA_temp [31:0];

 

assign temp_data [31:0] = DATA [31:0];

 

 

initial

begin

//second operation is read

#0 RD = 1'b1;

@(posedge ready);

repeat (9) @(posedge clk);

RD = 1'b0;

repeat (4) @(posedge clk);

RD = 1'b1;

//fourth operation is read after 4 writes

repeat (burst_length + 1) @(posedge ready); // For burst_length = 1,2,4,8,6

repeat (9) @(posedge clk);

RD = 1'b0;

repeat (4) @(posedge clk);

RD = 1'b1;

end

 

initial

begin

// first operation is write

#0 ADDR = 25'h0_0000_00;

@(posedge reset);

@(posedge clk);

@(posedge clk);

ADDR = 25'h0_4000_00;

repeat (1) @(posedge clk);

ADDR = 25'h0_0001_00;

repeat (3) @(posedge clk);

ADDR = 25'h0_0000_00;

// second operation is read

@(posedge ready);

repeat (9) @(posedge clk);

ADDR = 25'h0_4000_00;

@(posedge clk);

ADDR = 25'h0_000100;

repeat (3) @(posedge clk);

ADDR = 25'h0_0000_00;

//third operation is burst writes

@(posedge ready);

for(k=0;k<burst_length;k=i+1) begin

repeat (9) @(posedge clk);

ADDR = 25'h0_5800_00;

@(posedge clk);

ADDR = ADDR_store;

repeat (3) @(posedge clk);

ADDR = 25'h0_0000_00;

@(posedge ready);

ADDR_store = ADDR_store + 1;

end

// fourth operation read after 4 writes

repeat (9) @(posedge clk);

ADDR = 25'h0_5800_00;

@(posedge clk);

ADDR = 25'h018_56A1;

repeat (3) @(posedge clk);

ADDR = 25'h0_0000_00;

// opcode operations

@(negedge ready);

repeat (5) @(posedge clk);

ADDR = 25'h0_8000_00;

@(posedge clk);

ADDR = 25'h0_0000_00;

repeat (6) @(posedge clk);

ADDR = 25'h0_C000_00;

@(posedge clk);

ADDR = 25'h0_0000_00;

@(negedge ready);

ADDR = 25'h1_0000_00;

@(posedge clk);

ADDR = 25'h0_0000_00;

repeat (4) @(posedge clk);

ADDR = 25'h1_4000_00;

@(posedge clk);

ADDR = 25'h0_0000_00;

@(negedge ready);

ADDR = 25'h1_8000_00;

@(posedge clk);

ADDR = 25'h0_0000_00;

@(negedge ready);

ADDR = 25'h1_C000_00;

@(posedge clk);

ADDR = 25'h0_0000_00;

end

 

 

 

initial begin

$dumpfile("/scratch/proc.dump");

$dumpvars;

end

 

initial

#7000 $finish;

 

endmodule