module read_write(
// Inputs
clk, // System clock
reset, // Master reset
WR, // From Processor
RD, // From Processor
CS, // From Processor
ADDR, // From Processor
DATA, // From Processor
// Controller main outputs
RAS_L,
CAS_L,
WE_L,
CKE,
BS,
CSA_L,
CSB_L,
CSC_L,
CSD_L,
ready,
address_to_dram,
data_to_dram);
/*****************************************************************/
input clk; // System clock
input reset; // Reset
input CS; // Chip select
input WR; // Processor Write
input RD; // Processor Read
input [24:0] ADDR; // Address from Processor
inout [31:0] DATA; // Data from Processor
// count0; // Count value = 0
// count0_precharge;
// [3:0] chip_select_info; // chip select info stored
in the srorage register.
// refresh_entry_start;
// refresh_exit_start;
// power_down_entry_start;
// power_down_exit_start;
// burst_stop_start;
// nop_start;
// Trcd_count; // Control signal to load Trcd value in
the counter
output ready; // Control signal to the processor to send
the next instruction
// tRAS_count; // To down counter
// tRP_count; // To down counter
// tRC_ref_count; // To down counter
// latency2_count; // Control signal to laod latency
count
// latency3_count;
// burst_count2; // Control signal to burst value
// burst_count4;
// burst_count8;
// burst_full_count;
//CONTROLLER MAIN OUTPUTS
output RAS_L;
output CAS_L;
output WE_L;
output CSA_L;
output CSB_L;
output CSC_L;
output CSD_L;
output CKE;
output BS;
output [10:0] address_to_dram;
inout [31:0] data_to_dram;
/*****************************************************************/
reg [10:0] mode_reg;
reg latency_count;
reg burst_count;
reg ready;
reg [2:0] state, next_state;
reg [2:0] PD_state,PD_next_state;
reg [2:0] REF_state,REF_next_state;
reg [2:0] BANK_PRECHARGE_state,BANK_PRECHARGE_next_state;
reg [1:0] BURST_state,BURST_next_state;
reg [1:0] NOP_state,NOP_next_state;
reg [3:0] csa_csb_csc_csd_reg;
reg BS_reg1,BS_reg2;
reg [1:0] read_write_reg;
reg del_burst_count2;
reg del_burst_count4;
reg del_burst_count8;
reg del_burst_full_count;
reg [10:0] row_address;
reg [7:0] col_address;
reg [31:0] data_contr_in;
reg [7:0] LOADVALUE;
reg del_count0;
reg del_pre_count0;
reg [3:0] LOADVALUE_PRECHARGE;
reg burst_stop_start_2 , //delayed burst_stop_start
power_down_entry_start_2, //delayed power_down_entry_start
power_down_exit_start_2, //delayed power_down_exit_start
refresh_entry_start_2, //delayed refresh_entry_start
refresh_exit_start_2, //delayed refresh_exit_start
nop_start_2;
reg burst_stop_start, //final burst_stop_start
power_down_entry_start, //finel power_down_entry_start
power_down_exit_start, //final power_down_exit_start
refresh_entry_start, //final refresh_entry_start
refresh_exit_start, //final refresh_exit_start
nop_start;
wire [3:0] chip_select_info;
wire burst_stop_start_1, //not delayed burst_stop_start
power_down_entry_start_1, //not delayed power_down_entry_start
power_down_exit_start_1, //not delayed power_down_exit_start
refresh_entry_start_1, //not delayed refresh_entry_start
refresh_exit_start_1, //not delayed refresh_exit_start
nop_start_1;
wire [2:0] command_mode;
wire count0_precharge,count0_pre_temp;
wire count0, count0_temp;
wire precharge_start;
wire Trcd_count;
wire tRAS_count;
wire tRP_count;
wire tRC_ref_count;
wire burst_count2;
wire burst_count4;
wire burst_count8;
wire burst_full_count;
wire latency2_count;
wire latency3_count;
reg RAS_L;
reg CAS_L;
reg WE_L;
reg CSA_L;
reg CSB_L;
reg CSC_L;
reg CSD_L;
reg CKE;
reg BS;
wire [31:0] data_to_proc;
wire [31:0] data_to_dram;
wire [31:0] DATA;
// opcodes for command address decoder
parameter burst_stop_opcode = 3'b110,
power_down_entry_opcode = 3'b010,
power_down_exit_opcode = 3'b011,
refresh_entry_opcode = 3'b100,
refresh_exit_opcode = 3'b101,
nop_opcode = 3'b111;
//Read Write state machine states
parameter read_write_idle = 3'b000,
mode_reg_set_state = 3'b001,
bank_activate_state = 3'b010,
Trcd_wait_state = 3'b011,
read_state = 3'b100,
write_state = 3'b101,
wait_for_latency_state = 3'b110,
data_available_state = 3'b111;
//power down state machine states
parameter power_down_idle = 3'b000,
power_down_entry_start_state = 3'b001,
power_down_entry_cmd_state = 3'b010,
wait_for_PD_exit_state = 3'b011,
power_down_exit_cmd_state = 3'b100,
PD_NOP_state = 3'b101;
//self refresh state machine states
parameter refresh_idle = 3'b000,
refresh_entry_start_state = 3'b001,
refresh_entry_cmd_state = 3'b010,
wait_for_ref_exit_state = 3'b011,
refresh_exit_start_state = 3'b100,
refresh_exit_cmd_state = 3'b101,
Trc_wait_REF_state = 3'b110;
//burst stop state machine states
parameter burst_idle = 2'b00,
burst_stop_command = 2'b01,
burst_assert_ready = 2'b10;
//NOP state machine states
parameter nop_idle = 2'b00,
nop_command = 2'b01,
nop_assert_ready = 2'b10;
//Bank precharge state machine states
parameter precharge_idle = 3'b000,
precharge_load_tras = 3'b001,
wait_for_tras_state = 3'b010,
precharge_state = 3'b011,
wait_for_trp_state = 3'b100;
/*****************************************************************/
//*********** READ WRITE STATE MACHINE ******************************
always @(posedge clk) begin
if (!reset)
state <= read_write_idle;
else
state <= next_state;
end
always @(state or WR or RD or CS or count0 or read_write_reg
or mode_reg) begin
case (state)
read_write_idle : if ((!WR || !RD ) && !CS)
next_state <= mode_reg_set_state;
else
next_state <= read_write_idle;
mode_reg_set_state : next_state <= bank_activate_state;
bank_activate_state : next_state <= Trcd_wait_state;
Trcd_wait_state : if (count0 && (read_write_reg==2'b10))
next_state <= write_state;
else
if (count0 && (read_write_reg==2'b01))
next_state <= read_state;
else
next_state <= Trcd_wait_state;
write_state : if (count0 || (mode_reg[2:0] == 3'b000)
)
next_state <= read_write_idle;
else
next_state <= write_state;
read_state : if (mode_reg[6:4] == 3'b001)
next_state <= data_available_state;
else
next_state <= wait_for_latency_state;
wait_for_latency_state : if (count0)
next_state <= data_available_state;
else if (mode_reg[6:4] == 3'b010)
next_state <= data_available_state;
else if ((mode_reg[6:4] != 3'b010) && (mode_reg[6:4]
!= 3'b011))
next_state <= read_write_idle;
else
next_state <= wait_for_latency_state;
data_available_state : if (count0 || (mode_reg[2:0] ==
3'b000))
next_state <= read_write_idle;
else
next_state <= data_available_state;
default : next_state <= read_write_idle;
endcase
end
//******************* end of state machine *********************************
//storing the register values
always @(posedge clk) begin
if (~reset)
read_write_reg [1:0] <= 2'b00;
else
if (!RD && !CS)
read_write_reg [1:0] <= 2'b01;
else
if (!WR && !CS)
read_write_reg [1:0] <= 2'b10;
else
read_write_reg [1:0] <= read_write_reg [1:0];
end
always @(posedge clk) begin
if (!reset)
BS_reg1 <=0;
else
if ((!RD || !WR) && !CS)
BS_reg1 <= ADDR[19];
else
BS_reg1 <= BS_reg1;
end
always @(posedge clk) begin
if (!reset)
BS_reg2 <=0;
else
if ((state == data_available_state) || (state == write_state))
BS_reg2 <= BS_reg1;
else
BS_reg2 <= BS_reg2;
end
always @(posedge clk) begin
if (!reset)
csa_csb_csc_csd_reg <= 4'b0;
else
if ((!RD || !WR) && !CS)
csa_csb_csc_csd_reg <= chip_select_info;
else
csa_csb_csc_csd_reg <= csa_csb_csc_csd_reg;
end
always @(posedge clk) begin
if(!reset)
row_address [10:0] <= 11'b0;
else
if ((!RD || !WR) && !CS)
row_address [10:0] <= ADDR [18:8];
else
row_address [10:0] <= row_address [10:0];
end
always @(posedge clk) begin
if(!reset)
col_address [7:0] <= 8'b0;
else
if ((!RD || !WR) && !CS)
col_address [7:0] <= ADDR [7:0];
else
col_address [7:0] <= col_address [7:0];
end
always @(posedge clk) begin
if(~reset)
mode_reg [10:0] <= 11'b0000_0000_000;
else
if (~CS && (ADDR[24:22] == 3'b001))
mode_reg [10:0] <= DATA [10:0];
else
mode_reg [10:0] <= mode_reg [10:0];
end
//**************************** Power down state machine
************************
always @(posedge clk) begin
if (~reset)
PD_state <= power_down_idle;
else
PD_state <= PD_next_state;
end
always @(PD_state or power_down_entry_start or power_down_exit_start)
begin
case (PD_state)
power_down_idle : if (power_down_entry_start)
PD_next_state <= power_down_entry_start_state;
else
PD_next_state <= power_down_idle;
power_down_entry_start_state : PD_next_state <= power_down_entry_cmd_state;
power_down_entry_cmd_state : PD_next_state <= wait_for_PD_exit_state;
wait_for_PD_exit_state : if(power_down_exit_start)
PD_next_state <= power_down_exit_cmd_state;
else
PD_next_state <= wait_for_PD_exit_state;
power_down_exit_cmd_state : PD_next_state <= PD_NOP_state;
PD_NOP_state : PD_next_state <= power_down_idle;
default : PD_next_state <= power_down_idle;
endcase
end
/******************* end of PD_state machine *********************************/
/******************* Self refresh state machine *******************************/
always @(posedge clk) begin
if (~reset)
REF_state <= refresh_idle;
else
REF_state <= REF_next_state;
end
always @(REF_state or refresh_entry_start or refresh_exit_start
or count0) begin
case (REF_state)
refresh_idle : if (refresh_entry_start)
REF_next_state <= refresh_entry_start_state;
else
REF_next_state <= refresh_idle;
refresh_entry_start_state: REF_next_state <= refresh_entry_cmd_state;
refresh_entry_cmd_state : REF_next_state <= wait_for_ref_exit_state;
wait_for_ref_exit_state : if(refresh_exit_start)
REF_next_state <= refresh_exit_start_state;
else
REF_next_state <= wait_for_ref_exit_state;
refresh_exit_start_state : REF_next_state <= refresh_exit_cmd_state;
refresh_exit_cmd_state : REF_next_state <= Trc_wait_REF_state;
Trc_wait_REF_state : if (count0)
REF_next_state <= refresh_idle;
else
REF_next_state <= Trc_wait_REF_state;
default : REF_next_state <= refresh_idle;
endcase
end
//******************* end of REF_state machine *********************************
//******************* Burst stop state machine *********************************
always @(posedge clk) begin
if(~reset)
BURST_state <= burst_idle;
else
BURST_state <= BURST_next_state;
end
always @(BURST_state or burst_stop_start)begin
case (BURST_state)
burst_idle: if(burst_stop_start)
BURST_next_state <= burst_stop_command;
else
BURST_next_state <= burst_idle;
burst_stop_command: BURST_next_state <= burst_assert_ready;
burst_assert_ready: BURST_next_state <= burst_idle;
default : BURST_next_state <= burst_idle;
endcase
end
//****************************** end of burst stop state
machine *******************************
//****************************** Nop state machine ******************************
always @(posedge clk) begin
if(~reset)
NOP_state <= nop_idle;
else
NOP_state <= NOP_next_state;
end
always @(NOP_state or nop_start)begin
case (NOP_state)
nop_idle:
if(nop_start)
NOP_next_state <= nop_command;
else
NOP_next_state <= nop_idle;
nop_command:
NOP_next_state <= nop_assert_ready;
nop_assert_ready:
NOP_next_state <= nop_idle;
default :
NOP_next_state <= nop_idle;
endcase
end
//******************************** end of NOP state machine
************************************
//******************************** Bank Precharge state
machine ********************************
always @(posedge clk)begin
if(~reset)
BANK_PRECHARGE_state <= precharge_idle;
else
BANK_PRECHARGE_state <= BANK_PRECHARGE_next_state;
end
always @(BANK_PRECHARGE_state or precharge_start or count0_precharge)begin
case (BANK_PRECHARGE_state)
precharge_idle:
if (precharge_start)
BANK_PRECHARGE_next_state <= precharge_load_tras;
else
BANK_PRECHARGE_next_state <= precharge_idle;
precharge_load_tras:
BANK_PRECHARGE_next_state <= wait_for_tras_state;
wait_for_tras_state:
if(count0_precharge == 1'b1)
BANK_PRECHARGE_next_state <= precharge_state;
else
BANK_PRECHARGE_next_state <=wait_for_tras_state;
precharge_state:
BANK_PRECHARGE_next_state <= wait_for_trp_state;
wait_for_trp_state:
if(count0_precharge == 1'b1)
BANK_PRECHARGE_next_state <=precharge_idle;
else
BANK_PRECHARGE_next_state <=wait_for_trp_state;
default : BANK_PRECHARGE_next_state <=precharge_idle;
endcase
end
//******************************** end of bank precharge
state machine *************************
// asserting ready signal
always @(posedge clk)
begin
if((count0 && (REF_state == Trc_wait_REF_state))
||
(PD_state == PD_NOP_state) ||
(BURST_state == burst_assert_ready) ||
(NOP_state == nop_assert_ready) ||
(state == data_available_state && (count0 ||
mode_reg[2:0] == 3'b000) ) ||
(state == write_state && (count0 || mode_reg[2:0]
== 3'b000) )
)
ready <= 1'b1;
else
ready <= 1'b0;
end
//************************************** counter signals
*************************************
// asserting all the load signals for the counter
assign Trcd_count = (state == bank_activate_state);
assign tRAS_count = (BANK_PRECHARGE_state == precharge_load_tras);
assign tRC_ref_count = (REF_state == refresh_exit_cmd_state);
assign tRP_count = (BANK_PRECHARGE_state == precharge_state);
//assign latency2_count = ((state == read_state) &&
(mode_reg[6:4] == 3'b010));
assign latency3_count = ((state == read_state) &&
(mode_reg[6:4] == 3'b011));
assign burst_count2 =(((next_state == write_state) &&
(state != write_state) &&
(mode_reg[2:0] == 3'b001)) ||
((next_state == data_available_state) &&
(state != data_available_state) &&
(mode_reg[2:0] == 3'b001)) );
assign burst_count4 =(((next_state == write_state) &&
(state != write_state) &&
(mode_reg[2:0] == 3'b010)) ||
((next_state == data_available_state) &&
(state !=data_available_state) &&
(mode_reg[2:0] == 3'b010)) ) ;
assign burst_count8 =(((next_state == write_state) &&
(state != write_state) &&
(mode_reg[2:0] == 3'b011)) ||
((next_state == data_available_state) &&
(state !=data_available_state) &&
(mode_reg[2:0] == 3'b011)) );
assign burst_full_count =(((next_state == write_state)
&&
(state != write_state) &&
(mode_reg[2:0] == 3'b111)) ||
((next_state == data_available_state) &&
(state !=data_available_state) &&
(mode_reg[2:0] == 3'b111)) );
//START SIGNAL FOR THE BANK PRECHARGE STATE MACHINE
assign precharge_start = (state == bank_activate_state);
//****************************** OUTPUT SIGNALS OF THE
CONTROLLER ************************
always @(posedge clk) begin
if (~reset)
RAS_L <= 1'b1 ;
else if ((next_state == bank_activate_state) ||
(BANK_PRECHARGE_next_state == precharge_state ) ||
(next_state == mode_reg_set_state ) ||
(REF_next_state == refresh_entry_cmd_state) )
RAS_L <= 1'b0 ;
else
RAS_L <= 1'b1 ;
end
always @(posedge clk) begin
if (~reset)
CAS_L <= 1'b1 ;
else if ((next_state == write_state) ||
(next_state == read_state ) ||
(next_state == mode_reg_set_state ) ||
(REF_next_state == refresh_entry_cmd_state) )
CAS_L <= 1'b0 ;
else
CAS_L <= 1'b1 ;
end
always @(posedge clk) begin
if (~reset)
WE_L <= 1'b1 ;
else if ((BANK_PRECHARGE_next_state == precharge_state
) ||
(next_state == write_state) ||
(next_state == mode_reg_set_state ) ||
(PD_next_state == power_down_exit_cmd_state) ||
(BURST_next_state == burst_stop_command ) )
WE_L <= 1'b0 ;
else
WE_L <= 1'b1 ;
end
always @(posedge clk) begin
if (~reset)
CKE <= 1'b1;
else if
((REF_next_state == refresh_entry_start_state ) ||
(PD_next_state == power_down_entry_start_state) )
CKE <= 1'b0;
else if
((REF_next_state == refresh_exit_start_state ) ||
(PD_next_state == power_down_exit_cmd_state) )
CKE <= 1'b1;
else
CKE <= CKE ;
end
always @(posedge clk) begin
if (~reset)
CSA_L <= 1'b1 ;
else if( (next_state == mode_reg_set_state &&
chip_select_info == 4'b0111) ||
(next_state == write_state && csa_csb_csc_csd_reg
== 4'b0111) ||
(next_state == read_state && csa_csb_csc_csd_reg
== 4'b0111) ||
(BANK_PRECHARGE_next_state == precharge_state &&
csa_csb_csc_csd_reg == 4'b0111) ||
(next_state == bank_activate_state && csa_csb_csc_csd_reg
== 4'b0111) ||
(REF_next_state == refresh_entry_cmd_state ) ||
(REF_next_state == refresh_exit_cmd_state ) ||
(PD_next_state == power_down_entry_cmd_state ) ||
(PD_next_state == power_down_exit_cmd_state ) ||
(BURST_next_state == burst_stop_command && csa_csb_csc_csd_reg
== 4'b0111) ||
(NOP_next_state == nop_command && csa_csb_csc_csd_reg
== 4'b0111) )
CSA_L <= 1'b0 ;
else
CSA_L <= 1'b1 ;
end
always @(posedge clk) begin
if (~reset)
CSB_L <= 1'b1 ;
else if
( (next_state == mode_reg_set_state && chip_select_info
== 4'b1011) ||
(next_state == write_state && csa_csb_csc_csd_reg
== 4'b1011) ||
(next_state == read_state && csa_csb_csc_csd_reg
== 4'b1011) ||
(BANK_PRECHARGE_next_state == precharge_state &&
csa_csb_csc_csd_reg == 4'b1011) ||
(next_state == bank_activate_state && csa_csb_csc_csd_reg
== 4'b1011) ||
(REF_next_state == refresh_entry_cmd_state ) ||
(REF_next_state == refresh_exit_cmd_state ) ||
(PD_next_state == power_down_entry_cmd_state ) ||
(PD_next_state == power_down_exit_cmd_state ) ||
(BURST_next_state == burst_stop_command && csa_csb_csc_csd_reg
== 4'b1011) ||
(NOP_next_state == nop_command && csa_csb_csc_csd_reg
== 4'b1011) )
CSB_L <= 1'b0 ;
else
CSB_L <= 1'b1 ;
end
always @(posedge clk) begin
if (~reset)
CSC_L <= 1'b1 ;
else if
( (next_state == mode_reg_set_state && chip_select_info
== 4'b1101) ||
(next_state == write_state && csa_csb_csc_csd_reg
== 4'b1101) ||
(next_state == read_state && csa_csb_csc_csd_reg
== 4'b1101) ||
(BANK_PRECHARGE_next_state == precharge_state &&
csa_csb_csc_csd_reg == 4'b1101) ||
(next_state == bank_activate_state && csa_csb_csc_csd_reg
== 4'b1101) ||
(REF_next_state == refresh_entry_cmd_state ) ||
(REF_next_state == refresh_exit_cmd_state ) ||
(PD_next_state == power_down_entry_cmd_state ) ||
(PD_next_state == power_down_exit_cmd_state ) ||
(BURST_next_state == burst_stop_command && csa_csb_csc_csd_reg
== 4'b1101) ||
(NOP_next_state == nop_command && csa_csb_csc_csd_reg
== 4'b1101) )
CSC_L <= 1'b0 ;
else
CSC_L <= 1'b1 ;
end
always @(posedge clk) begin
if (~reset)
CSD_L <= 1'b1 ;
else if
( (next_state == mode_reg_set_state && chip_select_info
== 4'b1110) ||
(next_state == write_state && csa_csb_csc_csd_reg
== 4'b1110) ||
(next_state == read_state && csa_csb_csc_csd_reg
== 4'b1110) ||
(BANK_PRECHARGE_next_state == precharge_state &&
csa_csb_csc_csd_reg == 4'b1110) ||
(next_state == bank_activate_state && csa_csb_csc_csd_reg
== 4'b1110) ||
(REF_next_state == refresh_entry_cmd_state ) ||
(REF_next_state == refresh_exit_cmd_state ) ||
(PD_next_state == power_down_entry_cmd_state ) ||
(PD_next_state == power_down_exit_cmd_state ) ||
(BURST_next_state == burst_stop_command && csa_csb_csc_csd_reg
== 4'b1110) ||
(NOP_next_state == nop_command && csa_csb_csc_csd_reg
== 4'b1110) )
CSD_L <= 1'b0 ;
else
CSD_L <= 1'b1 ;
end
always @(posedge clk) begin
if (~reset)
BS <= BS_reg2 ;
else if
( (next_state == mode_reg_set_state ) ||
(next_state == write_state ) ||
(next_state == read_state ) ||
(next_state == bank_activate_state ) )
BS <= BS_reg1 ;
else
BS <= BS_reg2 ;
end
assign address_to_dram [10:0] = (state == mode_reg_set_state
) ? mode_reg [10:0] :
(state == bank_activate_state ) ? row_address[10:0] :
(state == read_state ) ? {3'b000,col_address[7:0]} :
(state == write_state ) ? {3'b010,col_address[7:0]} :
11'b000 ;
//******************* Tristate data Path **********************************************************
assign data_to_dram [31:0] = (state == write_state) ?
data_contr_in [31:0] : 32'hZZZZ_ZZZZ;
assign DATA [31:0] = (state == data_available_state)
? data_to_proc [31:0] : 32'hZZZZ_ZZZZ;
assign data_to_proc [31:0] = data_to_dram[31:0];
always @(posedge clk) begin
if (state == bank_activate_state)
data_contr_in [31:0] = DATA [31:0] ;
else
data_contr_in [31:0] = data_contr_in [31:0] ;
end
//************ Down counter to count the wait states
*****************************
always @(posedge clk)
if(!reset)
begin
LOADVALUE <= 255 ;
end
else
begin
if (Trcd_count)
LOADVALUE[7:0] <= 2;
else if (tRC_ref_count)
LOADVALUE[7:0] <= 9;
else if (latency3_count)
LOADVALUE[7:0] <= 1;
else if (burst_count2 )
LOADVALUE[7:0] <= 1;
else if (burst_count4 )
LOADVALUE[7:0] <= 3;
else if (burst_count8 )
LOADVALUE[7:0] <= 7;
else if (burst_full_count )
LOADVALUE[7:0] <= 5; // should be 255
else if (count0_temp)
LOADVALUE[7:0] <= LOADVALUE[7:0];
else
LOADVALUE[7:0] <= LOADVALUE[7:0] - 1;
end
assign count0_temp = (LOADVALUE == 8'b0);
always @(posedge clk) begin
if (!reset)
del_count0 <= 0;
else
del_count0 <= count0_temp;
end
assign count0 = (count0_temp && ~del_count0 );
//********************************************************************************
//*** precharge down counter for counting wait states
of bank precharge state machine ***
always @(posedge clk)
if(!reset)
begin
LOADVALUE_PRECHARGE <= 15 ;
end
else
begin
if (tRAS_count)
LOADVALUE_PRECHARGE[3:0] <= 9;
else if (tRP_count)
LOADVALUE_PRECHARGE[3:0] <= 2;
else if (count0_temp)
LOADVALUE_PRECHARGE[3:0] <= LOADVALUE_PRECHARGE[3:0];
else
LOADVALUE_PRECHARGE[3:0] <= LOADVALUE_PRECHARGE[3:0]
- 1;
end
assign count0_pre_temp = (LOADVALUE_PRECHARGE == 4'b0);
always @(posedge clk) begin
if (!reset)
del_pre_count0 <= 0;
else
del_pre_count0 <= count0_pre_temp;
end
assign count0_precharge = (count0_pre_temp &&
~del_pre_count0 );
//***************************************************************************************
//******** command address decoder to decode the starts
for different state machines ******
assign command_mode = (~CS && ((ADDR[24:22] ==
3'b001) ||
(ADDR[24:22] == 3'b000) )) ? 3'b000 : ADDR[24:22] ;
assign burst_stop_start_1 = (command_mode == burst_stop_opcode);
assign power_down_entry_start_1 = (command_mode == power_down_entry_opcode);
assign power_down_exit_start_1 = (command_mode == power_down_exit_opcode);
assign refresh_entry_start_1 = (command_mode == refresh_entry_opcode);
assign refresh_exit_start_1 = (command_mode == refresh_exit_opcode);
assign nop_start_1 = (command_mode == nop_opcode);
always @(posedge clk) begin
burst_stop_start_2 <= burst_stop_start_1;
end
always @(posedge clk) begin
power_down_entry_start_2 <= power_down_entry_start_1;
end
always @(posedge clk) begin
power_down_exit_start_2 <= power_down_exit_start_1;
end
always @(posedge clk) begin
refresh_entry_start_2 <= refresh_entry_start_1;
end
always @(posedge clk) begin
refresh_exit_start_2 <= refresh_exit_start_1;
end
always @(posedge clk) begin
nop_start_2 <= nop_start_1;
end
always @(posedge clk) begin
if (~reset) begin
burst_stop_start = 1'b0;
power_down_entry_start = 1'b0;
power_down_exit_start = 1'b0;
refresh_entry_start = 1'b0;
refresh_exit_start = 1'b0;
nop_start = 1'b0;
end
else begin
burst_stop_start = (!burst_stop_start_2 && burst_stop_start_1);
power_down_entry_start = (!power_down_entry_start_2 &&
power_down_entry_start_1);
power_down_exit_start = (!power_down_exit_start_2 &&
power_down_exit_start_1);
refresh_entry_start = (!refresh_entry_start_2 &&
refresh_entry_start_1);
refresh_exit_start = (!refresh_exit_start_2 &&
refresh_exit_start_1);
nop_start = (!nop_start_2 && nop_start_1);
end
end
//*******************************************************************************************
// ********* chip select decoder ***********************************************
assign chip_select_info = (ADDR[21:20] == 2'b00 &&
~CS) ? 4'b0111 :
(ADDR[21:20] == 2'b01 && ~CS) ? 4'b1011 :
(ADDR[21:20] == 2'b10 && ~CS) ? 4'b1101 :
(ADDR[21:20] == 2'b11 && ~CS) ? 4'b1110 : 4'b1111;
//********************************************************************************
endmodule