module tlb_ram (addr, data_wire,clk,we);

input [4:0] addr ;

inout [28:0] data_wire ;

input we ;

input clk ;

 

reg [28:0] mem[31:0] ;

wire [28:0] data_in, data_out ;

 

assign data_in = data_wire ;

assign data_out = mem[addr];

 

assign data_wire = (~we) ? data_out: 32'hZZZZ_ZZZZ;

 

always @(posedge clk)

begin

if(we ) begin

mem[addr] = data_in ;

//$display ("T:Addr = %x, T:DATA=%x",addr,data_in);

end

end

endmodule