module tb ();

reg clk, reset, inp_strb;

reg [29:0] inp; // rout_req_t

// 24 bits addr [28:5]

// 5 bits segment [4:0]

// 1 bit command 0 -> store, 1 -> find

wire busy;

wire outp_strb;

wire [28:0] outp; // tlb_entry_t

// 24 bits addr [28:5]

// 5 bits segment [4:0]

reg [23:0] testvectors [0:299]; // input memory (assume max 100 lines)

integer capture_vec; // output file

//ram interface

wire [4:0] t_addr ;

wire t_we;

wire [28:0] t_data ;

rt R1 (.clk(clk),

.reset(reset),

.inp_strb(inp_strb),

.inp(inp),

.busy(busy),

.outp_strb(outp_strb),

.outp(outp),

.t_data(t_data),

.t_addr(t_addr),

.t_we(t_we));

tlb_ram T1 (.addr(t_addr),

.data_wire(t_data),

.clk(clk),

.we(t_we));

initial begin

reset = 1'b1;

#950 reset = 1'b0;

capture_vec = $fopen("output.cap");

if (capture_vec == 0) begin

$display( "Could not open files");

$finish;

end

$readmemh("vecsv", testvectors, 0);

end

always begin: clkgen

clk = 1'b1;

forever begin

#100 clk = ~clk;

end

end

always begin : stimulate

integer i;

reg [23:0] tmp;

reg [29:0] req;

 

i = 0;

 

while (i < 100)

begin

inp_strb = 1'b0;

while ((busy !== 1'b0) && (reset !== 1'b0)) @(posedge clk) ; // handle x

if (testvectors[i] == 24'hffffff) begin // test for eof

#1000; $fclose(capture_vec); // wait for output before close

$stop;

end

req = 30'b0;

tmp = testvectors[i];

req[29] = tmp[0]; // opcode

i = i + 1;

req[28:5] = testvectors[i]; // address

i = i + 1;

if (req[29] == 1'b0) begin

tmp = testvectors[i];

req[4:0] = tmp[4:0];

i = i + 1;

end

inp = req;

@(posedge clk); #2;

inp_strb = 1'b1;

@(posedge busy); #2;

inp_strb = 1'b0;

@(posedge clk); #2;

end // while loop

end // stimulate

 

always begin : capture

@(negedge reset or outp_strb) ; #10;

$fdisplay( capture_vec, "%d, %x, %d", outp[28:5], outp[28:5], outp[4:0]);

end // capture

initial begin

/*$cw_display(reset);

$cw_display(clk);

$cw_display(inp_strb);

$cw_display(inp);

$cw_display(busy);

$cw_display(outp_strb);

$cw_display(outp);*/

$shm_open("waves.shm");

$shm_probe ("R1.*", R1, "R1.state.*", "*", clk,reset,inp_strb,inp,busy,outp_strb,outp);

#500000 $finish;

end

endmodule