module mmx_mem (addr, data_wire,clk,reset,we);

input [2:0] addr ;

inout [63:0] data_wire ;

input we ;

input clk ,reset;

reg [2:0] i;

reg [63:0] mem[0:7] ;

wire [63:0] data_in, data_out ;

 

assign data_in = data_wire ;

assign data_out = mem[addr];

 

assign data_wire = (~we) ? data_out: 64'hZZZZ_ZZZZ_ZZZZ_ZZZZ;

 

 

 

always @(posedge clk)

begin

if(reset) begin

mem[0] = 64'b0;

mem[1] = 64'b0;

mem[2] = 64'b0;

mem[3] = 64'b0;

mem[4] = 64'b0;

mem[5] = 64'b0;

mem[6] = 64'b0;

mem[7] = 64'b0;

end

else begin

if(we ) begin

mem[addr] = data_in ;

$display ("mmx:Addr = %x, mmx:DATA=%x",addr,data_in);

end

end

end

 

initial begin

$display ("mmx data out = %x",data_out);

end

 

endmodule