module main_mem (addr, data_wire,clk,we);

input [5:0] addr ;

inout [63:0] data_wire ;

input we ;

input clk ;

 

reg [63:0] mem [63:0] ;

wire [63:0] data_in, data_out ;

 

assign data_in = data_wire ;

assign data_out = mem[addr];

 

assign data_wire = (~we) ? data_out: 64'hZZZZ_ZZZZ_ZZZZ_ZZZZ;

 

initial begin

mem[0]= 64'h4000C00040004000;

mem[1]= 64'h2000000000002000;

mem[2]= 64'h1000000000001000;

mem[3]= 64'h2000000000002000;

mem[4]= 64'h4000000000004000;

mem[5]= 64'h6000C00040006000;

mem[6]= 64'h7000000000007000;

mem[7]= 64'h6000000000006000;

mem[8]= 64'h4000000000004000;

mem[9]= 64'h6000C00040006000;

mem[10]=64'h7000000000007000;

mem[11]=64'h6000000000006000; // End of Coefficients

mem[12]=64'h0000000000000000; // Beginning of Temp

mem[13]=64'h0000000000000000;

mem[14]=64'h0000000000000000;

mem[15]=64'h0000000000000000;

mem[16]=64'h0000000000000000;

mem[17]=64'h0000000000000000;

mem[18]=64'h0000000000000000;

mem[19]=64'h0000000000000000;

mem[20]=64'h0000000000000000;

mem[21]=64'h0000000000000000;

mem[22]=64'h0000000000000000;

mem[23]=64'h0000000000000000;

mem[24]=64'h0000000000000000; // End of Temp

mem[25]=64'h0000000000000000; // Beginning of data

mem[26]=64'h0000000000000000;

mem[27]=64'h0000000000000000;

mem[28]=64'h0000000000000000;

mem[29]=64'h0000000000000000;

mem[30]=64'h0000000000000000;

mem[31]=64'h0000000000000000;

mem[32]=64'h0000000000000000;

mem[33]=64'h0000000000000000;

mem[34]=64'h0000000000000000;

mem[35]=64'h0000000000000000;

mem[36]=64'h0000000000000000;

mem[37]=64'h0000000000000000;

mem[38]=64'h0000000000000000;

mem[39]=64'h0000000000000000;

mem[40]=64'h0000000000000000; // End of data

mem[41]=64'h0000000000000001; // NUMBERSHIFT value should be 1

mem[42]=64'h000000000000000E; // NUMBERSHIFT2 value should be 14

mem[43]=64'h4000400040004000; // SAMPLE

mem[44]=64'h0000000000000000;

mem[45]=64'h0000000000000000; //OUTPUT

mem[46]=64'h0000000000000000;

mem[47]=64'h0000000000000000;

mem[48]=64'h0000000000000000;

mem[49]=64'h0000000000000000;

mem[50]=64'h0000000000000000;

mem[51]=64'h0000000000000000;

mem[52]=64'h0000000000000000;

mem[53]=64'h0000000000000000;

mem[54]=64'h0000000000000000;

mem[55]=64'h0000000000000000;

mem[56]=64'h0000000000000000;

mem[57]=64'h0000000000000000;

mem[58]=64'h0000000000000000;

mem[59]=64'h0000000000000000;

mem[60]=64'h0000000000000000;

mem[61]=64'h0000000000000000;

mem[62]=64'h0000000000000000;

mem[63]=64'h0000000000000000;

 

end

 

 

always @(posedge clk)

begin

if(we ) begin

mem[addr] = data_in ;

$display ("main mem:Addr = %x, main mem :DATA=%x",addr,data_in);

end

end

endmodule