`include"idct.v"
`include"rams.v"
module testbench;
reg clk, reset, start;
reg [11:0] instream;
reg [11:0] sample;
wire [8:0] outstream;
wire done;
reg [3:0] i, j;
wire [5:0] o_addr;
wire [8:0] o_data;
wire o_we;
wire [4:0] c_addr;
wire [25:0] c_data;
wire [4:0] x_addr;
wire [23:0] x_data;
wire x_we;
wire [4:0] t_addr;
wire [31:0] t_data;
wire t_we;
idct fourier (.clk(clk),
.reset(reset),
.start(start),
.done(done),
.din(instream),
.dout(outstream),
.c_addr(c_addr),
.c_data(c_data),
.x_addr(x_addr),
.x_data(x_data),
.x_we(x_we),
.t_addr(t_addr),
.t_data(t_data),
.t_we(t_we),
.o_addr(o_addr),
.o_data(o_data),
.o_we(o_we));
c_rom C1 (.addr(c_addr),
.data(c_data));
x_ram X1 (.addr(x_addr),
.data_wire(x_data),
.clk(clk),
.we(x_we));
t_ram T1 (.addr(t_addr),
.data_wire(t_data),
.clk(clk),
.we(t_we));
o_ram O1 (.addr(o_addr),
.data_wire(o_data),
.clk(clk),
.we(o_we));
initial begin: po_reset
reset = 1'b1;
reset = #102 1'b0;
end
initial begin: clocking
clk = 1'b0;
forever begin
#50 clk = ~clk;
end
end
initial begin: stimulus
sample <= 12'hded;
@(posedge clk);
@(negedge reset);
start <= 1'b1;
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
if (i < 2 || i == 7) begin
sample = 12'h0;
end
else if (i == 2) begin
if (j == 0 || j == 6 || j == 7) begin
sample = 12'h0;
end else begin
sample = 12'h1ff;
end
end
else if (i == 3) begin
if (j == 2 || j == 5 || j == 6) begin
sample = 12'h1ff;
end else begin
sample = 12'h0;
end
end
else if (i == 4) begin
if (j == 2 || j == 5) begin
sample = 12'h1ff;
end else begin
sample = 12'h0;
end
end
else if (i == 5) begin
if (j < 2 || j > 5) begin
sample = 12'h0;
end else begin
sample = 12'h1ff;
end
end
else begin // i = 6
if (j == 3 || j ==4) begin
sample = 12'h1ff;
end else begin
sample = 12'h0;
end
end
instream <= sample;
@(posedge clk); #2;
end
end
sample <= 12'hded;
@(posedge clk);
@(posedge done);
start = 1'b1;
@(posedge clk);
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
@(posedge clk);
$display("out[%d][%d] = %x at %t", i, j, outstream,
$time);
end
end
$stop;
end
initial begin
/*$cw_display(clk);
$cw_display(reset);
$cw_display(start);
$cw_display(sample);
$cw_display(instream);
$cw_display(outstream);
$cw_display(done);
$cw_display(fourier.x_data);
$cw_display(fourier.main_state);
$cw_display(fourier.x_addr);
$cw_display(fourier.i);
$cw_display(fourier.j);
$cw_display(fourier.k);*/
$shm_open("test2.shm");
//$shm_probe ("fourier.*", fourier, "fourier.main_state.*",
"*", clk,reset,start,instream,outstream,done );
$shm_probe (fourier,clk,reset,start,instream,outstream,done
);
#200000 $finish;
end
endmodule