module comb_contr(clk,
reset,
mode,
idct_done,
fir_sample,
fir_result,
fir_start,
fir_done,
start,
din,
params,
dout,
ready,
iir_done,
iir_start,
start_for_idct,
done,
idct_start,
idct_din,
idct_dout,
c_addr,
c_data,
x_addr,
x_data,
x_we,
t_addr,
t_data,
t_we,
o_addr,
o_data,
o_we);
input clk, reset,start;
input [1:0] mode;
input [7:0] fir_sample;
output [9:0] fir_result;
output fir_done;
output fir_start;
 
//for iir
input [7:0] din;
output iir_done;
output iir_start;
input [15:0] params;
output [7:0] dout;
reg [7:0] dout;
output ready;
wire ready;
reg [6:0] finite_counter;
wire count0;
//wire iir_done;
reg del_count0;
//for idct
input start_for_idct;
input [11:0] idct_din;
output done,idct_done;
output [8:0] idct_dout;
output idct_start;
 
// C COEFFICENTS ROM INTERFACE (26x32)
input [25:0] c_data ;
output [4:0] c_addr ;
 
// X (D_IN) RAM INTERFACE (24x32)
inout [23:0] x_data ;
wire [23:0] x_data_out ;
output [4:0] x_addr ;
output x_we ;
wire x_we ;
wire [23:0] x_data ;
wire [23:0] x_data_in ;
 
// TRANSPOSE RAM INTERFACE (32x32)
inout [31:0] t_data ;
output [4:0] t_addr ;
output t_we ;
wire t_we;
wire [31:0] t_data ;
wire [31:0] t_data_out ;
wire [31:0] t_data_in;
 
 
// OUTPUT RAM INTERFACE (9x64)
inout [8:0] o_data ;
output [5:0] o_addr ;
output o_we ;
wire [8:0] o_data ;
wire [8:0] o_data_out;
wire [8:0] o_data_in;
wire o_we ;
 
reg [8:0] idct_dout;
wire done;
wire idct_done;
reg [1:0] k,j;
reg [2:0] i,j2;
reg [11:0] temp12;
reg [12:0] temp13a;
reg [12:0] temp13b;
reg [23:0] temp24;
reg [24:0] temp25a;
reg [24:0] temp25b;
reg [25:0] temp26;
reg [28:0] temp29;
reg [31:0] temp32;
//for controller
reg [2:0] cont_state;
reg [2:0] cont_nextstate;
reg fir_start,iir_start,idct_start;
 
parameter cont_idle =3'b000,
mode_select =3'b001,
state_idct =3'b010,
state_iir =3'b011,
state_fir =3'b100,
state_finish=3'b101;
 
// fir filter declarations
 
reg [9:0] fir_result;
reg [9:0] acc_temp;
reg [7:0] samp_latch;
reg [16:0] pro;
reg [18:0] acc;
reg [20:0] clk_cnt;
 
reg fir_done;
 
//iir filter declarations
 
reg [15:0] a1, a2, b0, b1, b2, yk1, yk2;
reg [7:0] uk, uk1, uk2 ;
reg [28:0] ysum ;
reg [26:0] yk ;
reg [22:0] utmp;
reg [3:0] wait_counter ;
// temporary variable
wire [31:0] yo1, yo2;
wire [23:0] b0t, b1t, b2t;
 
reg [3:0] state, next_state ;
parameter
idle = 0 ,
load_a2 = 2 ,
load_b0 = 3 ,
load_b1 = 4 ,
load_b2 = 5 ,
wait4_start = 6 ,
latch_din = 7 ,
compute_a = 8 ,
compute_b = 9 ,
compute_yk = 10 ,
wait4_count = 11 ,
latch_dout = 12 ;
//fir filter declarations
reg [7:0] shift_0,shift_1,shift_2,shift_3,shift_4,shift_5,shift_6,shift_7,shift_8,shift_9,shift_10,shift_11,shift_12,shift_13,shift_14,shift_15,shift_16;
parameter coefs_0=9'b111111001,coefs_1=9'b111111011,coefs_2=9'b000001101,
coefs_3=9'b000010000,coefs_4=9'b111101101,coefs_5=9'b111010110,
coefs_6=9'b000010111,coefs_7=9'b010011010,coefs_8=9'b011011110,
coefs_9=9'b010011010,coefs_10=9'b000010111,coefs_11=9'b111010110,
coefs_12=9'b111101101,coefs_13=9'b000010000,coefs_14=9'b000001101,
coefs_15=9'b111111011,coefs_16=9'b111111001;
//idct declarations
reg [4:0] main_state ;
reg [4:0] main_next_state ;
 
parameter
main_idle = 0 ,
load_x_ram = 1 ,
wrt_x_ram = 2 ,
wrt_x_ram_1 = 17 ,
transpose = 3 ,
wait4_trans_incrk = 4 ,
read_crom = 5 ,
read_xram1 = 6 ,
multiply_add1 = 7 ,
read_xram2 = 8 ,
multiply_add2 = 9 ,
multiply = 10 ,
read_tram = 11 ,
read_crom2 = 12 ,
multiply_add3 = 13 ,
wait4_mult_incrk = 14 ,
wait4_unload_start = 15 ,
wait4_unload = 16 ,
main_done = 18 ;
//CONTROLLER STATE MACHINE
always @(cont_state or fir_done or mode or idct_done or iir_done) begin
case(cont_state )
cont_idle : cont_nextstate <= mode_select;
mode_select : if (mode == 2'b01)
cont_nextstate <= state_idct;
else
if (mode == 2'b10)
cont_nextstate <= state_iir;
else
if (mode == 2'b11)
cont_nextstate <= state_fir;
else
cont_nextstate <= mode_select;
state_idct : if (idct_done)
cont_nextstate <= state_finish;
else
cont_nextstate <= state_idct;
state_iir : if (iir_done)
cont_nextstate <= state_finish;
else
cont_nextstate <= state_iir;
state_fir : if (fir_done)
cont_nextstate <= state_finish;
else
cont_nextstate <= state_fir;
state_finish : cont_nextstate <= cont_idle;
default : cont_nextstate <= cont_idle;
endcase
end
 
always @(posedge clk) begin
if (reset)
cont_state <= cont_idle;
else
cont_state <= cont_nextstate;
end
 
always @(posedge clk) begin
if (reset || (cont_state == state_finish))
idct_start <= 1'b0;
else
if (cont_state == state_idct)
idct_start <= 1'b1;
else
idct_start <= idct_start;
end
 
always @(posedge clk) begin
if (reset || (cont_state == state_finish))
iir_start <= 1'b0;
else
if (cont_state == state_iir)
iir_start <= 1'b1;
else
iir_start <= iir_start;
end
 
always @(posedge clk) begin
if (reset || (cont_state == state_finish))
fir_start <= 1'b0;
else
if (cont_state == state_fir)
fir_start <= 1'b1;
else
fir_start <= fir_start;
end
 
// ************************ FIR FILTER **********************************
 
function [16:0] mul_tc;
/* this is needed for twos complement multiplication */
input [7:0] A;
input [8:0] B;
reg sgn;
begin
sgn = A[7] ^ B[8];
if (A[7] == 1'b1) A = ~A + 1'b1;
if (B[8] == 1'b1) B = ~B + 1'b1;
mul_tc = A * B;
if (sgn == 1'b1) mul_tc = ~mul_tc + 1'b1;
end
endfunction
/**************************************************************************/
 
/****************counter to count 18 clock cycles**********************/
 
always @ (posedge clk)
begin
if(reset)
clk_cnt<={19'b000_0000_0000_0000_0000,1'b1};
else
if(fir_start)
clk_cnt<={clk_cnt[19:0],clk_cnt[20]};
else
clk_cnt<=clk_cnt;
end
/***********************************************************************/
 
/****************start of the fir filter operation*********************/
always @(posedge clk)
begin
if (reset) begin
shift_0<=8'h00;
shift_1<=8'h00;shift_2<=8'h00;shift_3<=8'h00;shift_4<=8'h00;shift_5<=8'h00;
shift_6<=8'h00;shift_7<=8'h00;shift_8<=8'h00;shift_9<=8'h00;shift_10<=8'h00;
shift_11<=8'h00;shift_12<=8'h00;shift_13<=8'h00;shift_14<=8'h00;shift_15<=8'h00;
shift_16<=8'h00;
samp_latch<=8'h00;
acc<=18'o000000;
pro<=17'h00000;
end
else begin
if(clk_cnt[0] && fir_start) begin
samp_latch<= fir_sample;
acc<=18'h0_0000;
end
else if(clk_cnt[1] && fir_start )
pro <= samp_latch*coefs_0;
else if (clk_cnt[2] && fir_start )
begin
//pro<= mul_tc(shift_15,coefs_16);
pro<=shift_15*coefs_16;
acc<={ pro[16], pro[16], pro };
shift_16<=shift_15;
end
else if (clk_cnt[3]&& fir_start )
begin
//pro<= mul_tc(shift_14,coefs_15);
pro<=shift_14*coefs_15;
acc<=acc+{ pro[16], pro[16], pro };
shift_15<=shift_14;
end
else if (clk_cnt[4]&& fir_start )
begin
//pro<= mul_tc(shift_13,coefs_14);
pro<=shift_13*coefs_14;
acc<=acc+{ pro[16], pro[16], pro };
shift_14<=shift_13;
end
else if (clk_cnt[5]&& fir_start )
begin
//pro<= mul_tc(shift_12,coefs_13);
pro<=shift_12*coefs_13;
acc<=acc+{ pro[16], pro[16], pro };
shift_13<=shift_12;
end
else if (clk_cnt[6]&& fir_start )
begin
//pro<= mul_tc(shift_11,coefs_12);
pro<=shift_11*coefs_12;
acc<=acc+{ pro[16], pro[16], pro };
shift_12<=shift_11;
end
else if (clk_cnt[7]&& fir_start )
begin
//pro<= mul_tc(shift_10,coefs_11);
pro<=shift_10*coefs_11;
acc<=acc+{ pro[16], pro[16], pro };
shift_11<=shift_10;
end
else if (clk_cnt[8]&& fir_start )
begin
//pro<= mul_tc(shift_9,coefs_10);
pro<=shift_9*coefs_10;
acc<=acc+{ pro[16], pro[16], pro };
shift_10<=shift_9;
end
else if (clk_cnt[9]&& fir_start )
begin
//pro<= mul_tc(shift_8,coefs_9);
pro<=shift_8*coefs_9;
acc<=acc+{ pro[16], pro[16], pro };
shift_9<=shift_8;
end
else if (clk_cnt[10]&& fir_start )
begin
//pro<= mul_tc(shift_7,coefs_8);
pro<=shift_7*coefs_8;
acc<=acc+{ pro[16], pro[16], pro };
shift_8<=shift_7;
end
else if (clk_cnt[11]&& fir_start )
begin
//pro<= mul_tc(shift_6,coefs_7);
pro<=shift_6*coefs_7;
acc<=acc+{ pro[16], pro[16], pro };
shift_7<=shift_6;
end
else if (clk_cnt[12]&& fir_start )
begin
//pro<= mul_tc(shift_5,coefs_6);
pro<=shift_5*coefs_6;
acc<=acc+{ pro[16], pro[16], pro };
shift_6<=shift_5;
end
else if (clk_cnt[13]&& fir_start )
begin
//pro<= mul_tc(shift_4,coefs_5);
pro<=shift_4*coefs_5;
acc<=acc+{ pro[16], pro[16], pro };
shift_5<=shift_4;
end
else if (clk_cnt[14]&& fir_start )
begin
//pro<= mul_tc(shift_3,coefs_4);
pro<=shift_3*coefs_4;
acc<=acc+{ pro[16], pro[16], pro };
shift_4<=shift_3;
end
else if (clk_cnt[15]&& fir_start )
begin
//pro<= mul_tc(shift_2,coefs_3);
pro<=shift_2*coefs_3;
acc<=acc+{ pro[16], pro[16], pro };
shift_3<=shift_2;
end
else if (clk_cnt[16]&& fir_start )
begin
//pro<= mul_tc(shift_1,coefs_2);
pro<=shift_1*coefs_2;
acc<=acc+{ pro[16], pro[16], pro };
shift_2<=shift_1;
end
else if (clk_cnt[17]&& fir_start )
begin
//pro<= mul_tc(shift_0,coefs_1);
pro<=shift_0*coefs_1;
acc<=acc+{ pro[16], pro[16], pro };
shift_1<=shift_0;
shift_0<=samp_latch;
end
else if (clk_cnt[18]&& fir_start )
begin
acc<=acc+{pro[16],pro[16],pro};
end
else
begin
shift_0<=shift_0;
shift_1<=shift_1;
shift_2<=shift_2;
shift_3<=shift_3;
shift_4<=shift_4;
shift_5<=shift_5;
shift_6<=shift_6;
shift_7<=shift_7;
shift_8<=shift_8;
shift_9<=shift_9;
shift_10<=shift_10;
shift_11<=shift_11;
shift_12<=shift_12;
shift_13<=shift_13;
shift_14<=shift_14;
shift_15<=shift_15;
shift_16<=shift_16;
samp_latch<=samp_latch;
acc<=acc;
pro<=pro;
end
end
end
always @ (posedge clk)
begin
if (reset)
fir_result<=10'h000;
else begin
if(clk_cnt[19]&& fir_start )
fir_result<=acc[18:9];
else
fir_result<=fir_result;
end
end
always @(posedge clk) begin
if (reset)
acc_temp[9:0]<=10'b0;
else begin
if(clk_cnt[0] && fir_start)
acc_temp[9:0]<=fir_result[9:0];
else
acc_temp[9:0]<=acc_temp[9:0];
end
end
 
always @(posedge clk) begin
if (reset)
fir_done <= 1'b0;
else
if(clk_cnt[20] && fir_start && (acc_temp==fir_result))
fir_done<=1'b1;
else
fir_done<=1'b0;
end
 
//********************************* IIR FILTER ****************************************************/
 
function [31:0] mul_tc_16_16;
input [15:0] A;
input [15:0] B;
input CLK;
reg sgn;
begin
sgn = A[15] ^ B[15];
if (A[15] == 1'b1) A = ~A + 1'b1;
if (B[15] == 1'b1) B = ~B + 1'b1;
mul_tc_16_16 = A * B;
if (sgn == 1'b1) mul_tc_16_16 = ~mul_tc_16_16 + 1'b1;
end
endfunction
 
function [23:0] mul_tc_8_16;
input [7:0] A;
input [15:0] B;
input CLK;
reg sgn;
begin
sgn = A[7] ^ B[15];
if (A[7] == 1'b1) A = ~A + 1'b1;
if (B[15] == 1'b1) B = ~B + 1'b1;
mul_tc_8_16 = A * B;
if (sgn == 1'b1) mul_tc_8_16 = ~mul_tc_8_16 + 1'b1;
end
endfunction
// STATE MACHINE
always @(posedge clk ) begin
if (reset || ~iir_start)
state <= idle ;
else
state <= next_state ;
end
 
always @(state or start or din or wait_counter or iir_start or count0)
begin
case (state )
idle : if (iir_start)
next_state <= load_a2 ;
else
next_state <= idle;
load_a2 : next_state <= load_b0 ;
load_b0 : next_state <= load_b1 ;
load_b1 : next_state <= load_b2 ;
load_b2 : next_state <= wait4_start ;
wait4_start : if (start)
next_state <= latch_din ;
else
next_state <= wait4_start ;
latch_din : next_state <= compute_a ;
compute_a : next_state <= compute_b ;
compute_b : next_state <= compute_yk ;
compute_yk : next_state <= wait4_count ;
wait4_count : if (wait_counter==0 )
next_state <= latch_dout ;
else
next_state <= wait4_count ;
 
latch_dout : if (count0)
next_state <= idle;
else
next_state <= wait4_start ;
default : next_state <= idle;
endcase
end
// END OF STATE MACHINE
 
 
assign yo1 = mul_tc_16_16(yk1, a1, clk);
assign yo2 = mul_tc_16_16(yk2, a2, clk);
assign b0t = mul_tc_8_16(uk, b0, clk);
assign b1t = mul_tc_8_16(uk1, b1, clk);
assign b2t = mul_tc_8_16(uk2, b2, clk);
assign ready = (state==wait4_start) ;
// A COEFFICENTS
always @(posedge clk or posedge reset) begin
if (reset ) begin
uk <= 0 ;
uk1 <= 0 ;
uk2 <= 0 ;
yk1 <= 0 ;
yk2 <= 0 ;
yk <= 0 ;
ysum <= 0 ;
utmp <= 0 ;
a1 <= 0 ;
a2 <= 0 ;
b0 <= 0 ;
b1 <= 0 ;
b2 <= 0 ;
dout <= 0 ;
end
else begin
if (state==compute_yk ) begin
uk1 <= uk ;
uk2 <= uk1 ;
yk <= ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp};
end
else begin
uk1 <= uk1 ;
uk2 <= uk2 ;
yk <= yk ;
end
 
if (state==wait4_start & start ) uk <= din ; else uk <= uk ;
if (state==idle ) a1 <= params ; else a1 <= a1 ;
if (state==load_a2 ) a2 <= params ; else a2 <= a2 ;
if (state==load_b0 ) b0 <= params ; else b0 <= b0 ;
if (state==load_b1 ) b1 <= params ; else b1 <= b1 ;
if (state==load_b2 ) b2 <= params ; else b2 <= b2 ;
 
if (state==compute_a )
ysum <= yo1[31:3] + yo2[31:3];
else
ysum <= ysum ;
 
if (state==compute_b )
utmp <= b0t[22:0] + b1t[22:0] + b2t[22:0];
else
utmp <= utmp ;
 
if (state==wait4_count && wait_counter==0) begin
dout <= yk[26:19];
yk1 <= yk[26:11] ;
yk2 <= yk1 ;
end
else begin
dout <= dout ;
yk1 <= yk1 ;
yk2 <= yk2 ;
end
end
end
 
 
// wait counter, count 4 clock after sum is calculated, to
// time outputs are ready, and filter is ready to accept next
// input
always @(posedge clk or posedge reset ) begin
if (reset )
wait_counter <= 0 ;
else begin
if (state==compute_yk )
wait_counter <= 4 ;
else if (state==wait4_count)
wait_counter <= wait_counter - 1;
else
wait_counter <= wait_counter ;
end
end
 
always @(posedge clk) begin
if (reset)
finite_counter<=100;
else
if (iir_start)
finite_counter<=finite_counter -1;
else
finite_counter<=finite_counter;
end
 
assign count0=finite_counter==7'b0;
 
always @(posedge clk) begin
del_count0 <= count0;
end
 
assign iir_done = (count0 && ~del_count0);
 
//******************************** IDCT START **********************************/
 
function [24:0] mult13_12;
/* twos complement multiplication */
input [12:0] A; // the port names A, B, Z
input [11:0] B; // are taken from the designWare
// otherwise this won't work
reg sgn;
// to one designWare function.
begin
// the following is only for simulation
sgn = A[12] ^ B[11];
if (A[12] == 1'b1) A = ~A + 1'b1;
if (B[11] == 1'b1) B = ~B + 1'b1;
mult13_12= A * B;
if (sgn == 1'b1) mult13_12 = ~mult13_12 + 1'b1;
end
endfunction
 
function [24:0] mult13_16;
/* twos complement multiplication */
input [12:0] A; // the port names A, B, Z
input [15:0] B; // are taken from the designWare
// otherwise this won't work
reg sgn;
begin
// the following is only for simulation
sgn = A[12] ^ B[15];
if (A[12] == 1'b1) A = ~A + 1'b1;
if (B[15] == 1'b1) B = ~B + 1'b1;
mult13_16 = A * B;
if (sgn == 1'b1) mult13_16 = ~mult13_16 + 1'b1;
end
endfunction
 
 
//idct state machine
//***************************************************************************************************/
always @(start_for_idct or main_state or i or j or k or j2 ) begin
case(main_state )
main_idle : if (start_for_idct && idct_start )
main_next_state <= load_x_ram ;
else
main_next_state <= main_idle ;
 
load_x_ram : main_next_state <= wrt_x_ram_1 ;
 
wrt_x_ram_1 : main_next_state <= wrt_x_ram ;
 
wrt_x_ram : if((j==3) && (i==7))
main_next_state <= transpose ;
else
main_next_state <= wrt_x_ram_1 ;
 
transpose : main_next_state <=read_crom;
 
read_crom : main_next_state <= read_xram1;
read_xram1 : main_next_state <= multiply_add1;
multiply_add1 : main_next_state <= read_xram2;
read_xram2 : main_next_state <= multiply_add2;
multiply_add2 : main_next_state <= wait4_trans_incrk;
wait4_trans_incrk : if ((k==3) && (j==3) && (i==7))
main_next_state <= multiply ;
else
main_next_state <= read_crom ;
multiply : main_next_state <=read_tram ;
 
wait4_mult_incrk : if ((k==3) && (j2==7) && (i==7))
main_next_state <=wait4_unload_start ;
else
main_next_state <= read_tram ;
read_tram : main_next_state <= read_crom2 ;
read_crom2 : main_next_state <= multiply_add3 ;
multiply_add3 : main_next_state <= wait4_mult_incrk ;
 
wait4_unload_start: if (start_for_idct)
main_next_state <= wait4_unload ;
else
main_next_state <= wait4_unload_start ;
wait4_unload : if ((i==7)&&(j2==7)) main_next_state <= main_done ;
else
main_next_state <= wait4_unload ;
main_done : main_next_state <= main_idle ;
default : main_next_state <= main_idle ;
endcase
end
 
always @(posedge clk )
begin
if (reset )
main_state <= main_idle ;
else
main_state <= main_next_state ;
end
//-------------------------------------------------------------------
// i counter
// outer for loop
always @(posedge clk )
begin
if (reset )
i <= 3'b0;
/* initialize before counting */
else if ((main_state==load_x_ram) |
(main_state==transpose) |
(main_state==multiply) |
(main_state==wait4_unload_start))
i <= 3'b0;
else if(((j==3) && (main_state==wrt_x_ram ))|
((j==3) && (k==3) && (main_state==wait4_trans_incrk))|
((j2==7) && (k==3) && (main_state==wait4_mult_incrk ))|
((j2==7) && (main_state==wait4_unload)))
i <=i+1;
else
i <= i ;
end
//-------------------------------------------------------------------
// j counter
// second inner for loop
always @(posedge clk )
begin
if (reset )
j <= 2'b0;
else if ((main_state==load_x_ram) |
(main_state==transpose))
j <= 2'b0 ;
/* transpose and second multiplication have inner k loops */
else if((main_state==wrt_x_ram) |
((main_state==wait4_trans_incrk) && (k==3) ) )
j <=j+1;
else
j <= j ;
end
 
 
//-------------------------------------------------------------------
// j2 counter
// second inner for loop
always @(posedge clk )
begin
if (reset )
j2 <= 3'b0;
/* initialize before counting */
else if ((main_state==multiply) |
(main_state==wait4_unload_start))
j2 <= 3'b0 ;
/* transpose and second multiplication have inner k loops */
else if(((main_state==wait4_mult_incrk) && (k==3)) |
(main_state==wait4_unload))
j2 <=j2+1;
else
j2 <= j2 ;
end
 
//---------------------------------------------------------------------
 
// k counter
// inner most loop
 
always @(posedge clk )
begin
if (reset )
k <= 2'b0;
/* initialize before counting */
else if ((main_state==load_x_ram) |
(main_state==transpose) |
(main_state==multiply))
k <= 2'b0 ;
else if((main_state==wait4_trans_incrk) |
(main_state==wait4_mult_incrk) )
k <=k+1;
else
k <= k ;
end
 
//-------------------------------------------------------------------
assign x_addr =(main_state==read_xram1)? 4*(j*2)+k :(main_state==read_xram2)? 4 * (j * 2 + 1) + k : 4*i+j ;
assign t_addr =(main_state==read_tram) ? 4*j2+k : 4*i+j ;
assign o_addr = 8*i+j2 ;
/*
assign c_addr =((main_state==read_crom)|
(main_state==read_crom2))? 4*i+k : 4*i+j ;
*/
assign c_addr = 4*i+k ;
 
//___________________________________________________________________
 
always @ (posedge clk)
temp12<=idct_din;
assign x_we= (main_state==wrt_x_ram_1) ? 1'b1: 1'b0;
assign x_data_in={temp12,idct_din}; //for writing into x_ram
assign x_data = (x_we)? x_data_in : 24'hZZZZZZ;
assign x_data_out = x_data;
//___________________________________________________________________
//transpose and first multiplication
always @ (posedge clk)
begin
if (reset ) begin
temp26 <= 0 ;
end
else if (main_state==read_crom | main_state ==read_crom2) begin
temp26 <= c_data;
end
else begin
temp26 <= temp26;
end
if (main_state==read_xram1) begin
temp24 <= x_data_out;//addr is different here check out
end
else if (main_state==read_xram2) begin
temp24 <= x_data_out;//check the addr here
end
else begin
temp24 <= temp24;
end
end
always @ (posedge clk)
if (reset ) begin
temp25a <= 0 ;
end
//else if ((main_state==read_crom) && (k==3)) begin
else if ((main_state==wait4_trans_incrk) && (k==3)) begin
temp25a <= 0;
end
else if (main_state==multiply_add1) begin
temp25a <= temp25a + mult13_12(temp26[25:13], temp24[23:12]) +
mult13_12(temp26[12:0], temp24[11:0]);
end
else begin
temp25a <=temp25a ;
end
always @ (posedge clk)
if (reset ) begin
temp25b <= 0 ;
end
//else if ((main_state==read_crom) && (k==3)) begin
else if ((main_state==wait4_trans_incrk) && (k==3)) begin
temp25b <= 0;
end
else if (main_state==multiply_add2) begin
temp25b <= temp25b + mult13_12(temp26[25:13], temp24[23:12]) +
mult13_12(temp26[12:0], temp24[11:0]);
end
else begin
temp25b <=temp25b ;
end
 
//debug
//initial
//$monitor ("temp26=%x,temp24=%x,temp25a=%x,temp25b=%x,i=%x,j=%x,k=%x",temp26,temp24,temp25a,temp25b,i,j,k);
 
//______________________________________________________________________
//writing into the t-ram
 
assign t_data_in ={temp25a[23:8], temp25b[23:8]};
assign t_we= ((k==3) && (main_state==wait4_trans_incrk))? 1'b1:1'b0;
assign t_data = (t_we)? t_data_in : 32'hZZZZ_ZZZZ;
assign t_data_out = t_data;
//____________________________________________________________________
 
//second multiplication and transpose
 
//reading t_ram
always @ (posedge clk)
if (reset)
temp32<=0;
else
if (main_state==read_tram)
temp32<=t_data_out;
else
temp32<=temp32;
/*//reading the crom again for second time
always @ (posedge clk)
if (main_state==read_crom2)
temp26<= c_data;
else
temp26<= temp26;*/
//multiply and adding
always @ (posedge clk)
if (((main_state == wait4_mult_incrk) && (k==3)) | (main_state==multiply) )
temp29<=0;
else
if (main_state == multiply_add3)
temp29 <= temp29 + mult13_16(temp26[25:13], temp32[31:16]) +
mult13_16(temp26[12:0], temp32[15:0]);
else
temp29 <= temp29 ;
//loading output ram
assign o_we=((main_state == wait4_mult_incrk) && (k==3))? 1'b1:1'b0;
 
assign o_data_in = temp29[26:18];
assign o_data = (o_we)? o_data_in : 9'hZZZ;
assign o_data_out = o_data;
 
//____________________________________________________________________________
// writing the results out
 
always @ (posedge clk)
if (main_state == wait4_unload)
idct_dout<= o_data;
else
idct_dout<= idct_dout;
 
//________________________________________________________________________
 
//asserting and deasserting done
assign done = (main_state==wait4_unload)? 1'b1:1'b0;
assign idct_done = (main_state==main_done) ? 1'b1:1'b0;
//________________________________________________________________________
 
endmodule