`include"rams.v"
module tb ();
reg clk, reset;
reg [7:0] instream;
wire [9:0] outstream;
reg [1:0] mode;
wire fir_start;
wire fir_done;
//for iir
reg rrset,start;
reg [7:0] din;
reg [15:0] params;
wire [7:0] dout;
wire [7:0] routstream;
wire ready, rready;
wire iir_done;
wire iir_start;
//for idct
reg start_for_idct;
reg [11:0] idct_instream;
reg [11:0] idct_sample;
wire [8:0] idct_outstream;
wire done,idct_done;
reg [3:0] i, j;
wire idct_start;
wire [5:0] o_addr;
wire [8:0] o_data;
wire o_we;
wire [4:0] c_addr;
wire [25:0] c_data;
wire [4:0] x_addr;
wire [23:0] x_data;
wire x_we;
wire [4:0] t_addr;
wire [31:0] t_data;
wire t_we;
comb_contr filter (.clk(clk),
.reset(reset),
.mode(mode),
.fir_sample(instream),
.fir_result(outstream),
.fir_start(fir_start),
.fir_done(fir_done),
.start(start),
.din(din),
.params(params),
.dout(dout),
.ready(ready),
.iir_done(iir_done),
.iir_start(iir_start),
.start_for_idct(start_for_idct),
.done(done),
.idct_start(idct_start),
.idct_done(idct_done),
.idct_din(idct_instream),
.idct_dout(idct_outstream),
.c_addr(c_addr),
.c_data(c_data),
.x_addr(x_addr),
.x_data(x_data),
.x_we(x_we),
.t_addr(t_addr),
.t_data(t_data),
.t_we(t_we),
.o_addr(o_addr),
.o_data(o_data),
.o_we(o_we));
c_rom C1 (.addr(c_addr),
.data(c_data));
x_ram X1 (.addr(x_addr),
.data_wire(x_data),
.clk(clk),
.we(x_we));
t_ram T1 (.addr(t_addr),
.data_wire(t_data),
.clk(clk),
.we(t_we));
o_ram O1 (.addr(o_addr),
.data_wire(o_data),
.clk(clk),
.we(o_we));
initial begin: po_reset
reset = 1'b1;
reset = #102 1'b0;
@(negedge fir_done);
repeat(2) @(posedge clk);
//for iir
reset = 1'b1;
rrset = 1'b1;
#100;
rrset = #2 1'b0;
#50;
reset = #2 1'b0;
//for idct
@(negedge iir_start);
repeat(2) @(posedge clk);
reset = 1'b1;
reset = #102 1'b0;
end
always begin: clkgen
clk = 1'b1;
forever begin
#25 clk = ~clk;
end
end
initial begin
#0 mode = 0;
#150 mode = 2'b11;//for fir
#300 mode =0;
@(negedge fir_done);
repeat(2) @(posedge clk);
#150 mode = 2'b10;//for iir
#300 mode =0;
@(negedge iir_start);
repeat(2) @(posedge clk);
#150 mode = 2'b01;//for idct
#300 mode =0;
end
initial begin:stimulus // impulse function for fir
#0 instream = 8'h0;
@(posedge fir_start);
#2; // skew wrt clk
instream = 8'h80;
end
initial begin: stimulus_iir// this is for iir
@(posedge iir_start);
start = 1'b0;
din = 8'h0;
params = 16'h2CF9; // a1
@(posedge clk); #2;
params = 16'hD5CE; // a2
@(posedge clk); #2;
params = 16'h1BE6; // b0
@(posedge clk); #2;
params = 16'h37CD; // b1
@(posedge clk); #2;
params = 16'h1BE6; // b2
@(posedge ready); #2;
start = 1'b1;
din = 8'h60; // impulse input
@(negedge ready); #2;
start = 1'b0;
din = 8'h0;
forever begin
@(posedge ready); #2
#2 start = 1'b1;
@(negedge ready); #2
#2 start = 1'b0;
end
end
initial begin: stimulus_idct //for idct
@(posedge idct_start);
idct_sample <= 12'hded;
@(posedge clk);
start_for_idct <= 1'b1;
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
if (i < 2 || i == 7) begin
idct_sample = 12'h0;
end
else if (i == 2) begin
if (j == 0 || j == 6 || j == 7) begin
idct_sample = 12'h0;
end else begin
idct_sample = 12'h1ff;
end
end
else if (i == 3) begin
if (j == 2 || j == 5 || j == 6) begin
idct_sample = 12'h1ff;
end else begin
idct_sample = 12'h0;
end
end
else if (i == 4) begin
if (j == 2 || j == 5) begin
idct_sample = 12'h1ff;
end else begin
idct_sample = 12'h0;
end
end
else if (i == 5) begin
if (j < 2 || j > 5) begin
idct_sample = 12'h0;
end else begin
idct_sample = 12'h1ff;
end
end
else begin // i = 6
if (j == 3 || j ==4) begin
idct_sample = 12'h1ff;
end else begin
idct_sample = 12'h0;
end
end
idct_instream <= idct_sample;
@(posedge clk); #2;
end
end
idct_sample <= 12'hded;
@(posedge clk);
@(posedge done);
start_for_idct = 1'b1;
@(posedge clk);
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
@(posedge clk);
$display("out[%d][%d] = %x at %t", i, j, idct_outstream,
$time);
end
end
//$stop;
end
initial begin
$monitor("clk %d,reset %d, input %x, output %x",clk,reset,instream,outstream);
#200000 $finish;
end
initial begin
$dumpfile("/scratch/comb.dump");
$dumpvars;
end
endmodule