module test;

 

parameter DATA_LENGTH = 160;

parameter DATA_LENGTH2 = 128;

reg reset, clk, eop_phy, data_start, subact_gap, phys_arb,

async_data_strt, data_end, data_prefix;

wire in ;

 

 

 

reg [7:0] data_ptr;

reg [0: DATA_LENGTH - 1] DATA;

reg [0: DATA_LENGTH2 - 1] DATA2;

reg data_switch;

wire [15:0] isodat_len_latch;

wire [31:0] isodata_latch;

wire [3:0] isotcode_latch;

wire [31:0] cycle_quad;

wire [15:0] cyc_src_id_latch;

wire [31:0] cyc_dest_off_latch;

wire [31:0] cyc_tim_data_latch;

 

 

 

iso_main M1(.reset(reset),.clk(clk),.in(in),.eop_phy(eop_phy),.data_start(data_start),

.subact_gap(subact_gap),

.isodat_len_latch(isodat_len_latch),

.isotcode_latch(isotcode_latch),

.isodata_latch(isodata_latch),

.phys_arb(phys_arb),

.async_data_strt(async_data_strt),

.data_end(data_end),

.data_prefix(data_prefix),

.cycle_quad(cycle_quad),

.async_enab(async_enab),

.cyc_src_id_latch(cyc_src_id_latch),

.cyc_dest_off_latch(cyc_dest_off_latch),

.cyc_tim_data_latch(cyc_tim_data_latch));

// CLOCK BLOCK

initial begin

clk = 1'b0;

forever #180 clk = ~clk;

end

// RESET BLOCK

initial begin

reset = 'b0;

@(posedge clk ) #1 reset = 1'b1 ;

repeat (3) @(posedge clk); // make reset active for 3 clocks

@(posedge clk ) #1 reset = 1'b0 ;

end

 

initial begin

// INITIAL EVERYTHING TO DEFAULT VALUES

{phys_arb, async_data_strt,data_end, data_prefix} = 4'b0000;

{eop_phy,data_start,subact_gap}=3'b000;

{phys_arb, async_data_strt,data_end, data_prefix} = 4'b0000;

data_ptr = 0;

data_switch = 1'b1 ;

DATA = 160'hFFFF004FFFFF0156135756217314972106917045;

// WAIT FOR REST AND START TESTS

repeat (10) @(posedge clk);

// START TEST HERE

 

repeat (2) @(posedge clk ); // ASSERT PHYS_ARB

#2 {phys_arb, async_data_strt,data_end, data_prefix} = 4'b1000;

repeat (1) @(posedge clk );// DEASSERT PHYS_ARB AFTER 1 CLOCK

#2 {phys_arb, async_data_strt,data_end, data_prefix} = 4'b0000;

 

repeat (1) @(posedge clk ); // ASSERT ASYNC_DATA_START & RESET POINTERS

#2 {phys_arb, async_data_strt,data_end, data_prefix} = 4'b0100;

data_ptr = 0;

repeat (1) @(posedge clk ); // DEASSERT ASYNC_DATA_START

#2 {phys_arb, async_data_strt,data_end, data_prefix} = 4'b0000;

 

repeat (200) @(posedge clk); //AFTER 100 CLOCKS ASSERT DATA_END & DATA_PREFIX

#2 {phys_arb, async_data_strt,data_end, data_prefix} = 4'b0011;

repeat (1) @(posedge clk); // DEASSERT DATA_END & DATA_PREFIX

#2 {phys_arb, async_data_strt,data_end, data_prefix} = 4'b0000;

 

// INITIALIZE FOR SECOND PACKET

repeat (1) @(posedge clk );

#2 {eop_phy,data_start,subact_gap}=3'b000;

data_ptr = 0;

DATA2 = 128'h001001A9248E8D293AC7B0DF642A5F29;

 

repeat (1) @(posedge clk ); // ASSET DATA_START

#2 {eop_phy,data_start,subact_gap}=3'b010;

data_switch = 0;

repeat (1) @(posedge clk ); // ASSET DATA_START

#2 {eop_phy,data_start,subact_gap}=3'b000;

 

repeat (90) @(posedge clk);

#2 {eop_phy,data_start,subact_gap}=3'b100;

repeat (1) @(posedge clk);

#2 {eop_phy,data_start,subact_gap}=3'b000;

 

repeat (1) @(posedge clk); // ASSERT SUB_ACTION_GAP

#2 {eop_phy,data_start,subact_gap}=3'b001;

repeat (1) @(posedge clk);

#2 {eop_phy,data_start,subact_gap}=3'b000;

end

assign in = (data_switch ) ? DATA[data_ptr] : DATA2[data_ptr];

always@(posedge clk) begin

if (reset | async_data_strt | data_start)

#2 data_ptr = 0 ;

else

#2 data_ptr = data_ptr + 1;

end

 

 

initial begin

 

$shm_open("waves.shm");

$shm_probe ("M1.*", M1, "M1.main_state.*","M1.rx_iso_state.*","*", clk, reset,in,phys_arb,async_data_strt,data_end,data_prefix,data_start,eop_phy,subact_gap);

 

#150000 $finish;

end

endmodule