module tb ();

 

reg clock, reset;

reg [7:0] instream;

wire [9:0] outstream;

reg fir_start;

wire fir_done;

 

 

fir2 filter (clock, reset, instream, outstream);

 

initial begin: po_reset

reset = 1'b1;

reset = #102 1'b0;

end

initial begin

#0 fir_start = 1'b0;

#150 fir_start = 1'b1;

end

always @(posedge clock)

if(fir_done==1'b1) fir_start = 1'b0;

 

always begin: clockgen

clock = 1'b1;

forever begin

#25 clock = ~clock;

end

end

 

initial begin: stimulus // impulse function

#2; // skew wrt clock

instream = 8'h0;

#100; // after the reset

instream = 8'h80;

// #50;

// instream = 8'h0;

end

 

initial begin

$shm_open("comb.shm");

$shm_probe ("filter.*",filter,"filter.clk_cnt.*","*",clock, reset, instream, outstream,fir_start,fir_done);

#20000 $finish;

end

 

//$monitor("clock %d,reset %d, input %x, output %x",clock,reset,instream,outstream);

 

 

endmodule