module t_ram (addr, data_wire,clk,we);

input [4:0] addr ;

inout [31:0] data_wire ;

input we ;

input clk ;

 

reg [31:0] mem[31:0] ;

wire [31:0] data_in, data_out ;

 

assign data_in = data_wire ;

assign data_out = mem[addr];

 

assign data_wire = (~we) ? data_out: 32'hZZZZ_ZZZZ;

 

always @(posedge clk)

begin

if(we ) begin

mem[addr] = data_in ;

//$display ("T:Addr = %x, T:DATA=%x",addr,data_in);

end

end

endmodule

 

 

 

// implementing a 26 word 32 wide ROM

module c_rom (addr, data);

input [4:0] addr ;

output [25:0] data ;

reg [25:0] mem[31:0] ;

reg [12:0] temp13a, temp13b ;

integer i, j ;

 

initial begin

for (i = 0; i < 8; i = i + 1) begin

for (j = 0; j < 4; j = j + 1) begin

if (i == j * 2) temp13a = 13'h0800;

else temp13a = 13'h0000;

if (i == j * 2 + 1) temp13b = 13'h0800;

else temp13b = 13'h0000;

mem[4 * i + j] = {temp13a, temp13b};

end

end

end

// read

assign data = mem[addr] ;

endmodule

 

 

 

module o_ram (addr, data_wire,clk,we);

input [5:0] addr ;

inout [8:0] data_wire ;

input we ;

input clk ;

 

reg [8:0] mem[63:0] ;

wire [8:0] data_in, data_out ;

 

assign data_in = data_wire ;

assign data_out = mem[addr];

 

assign data_wire = (~we) ? data_out: 9'hZZZ;

always @(posedge clk)

begin

if(we ) begin

mem[addr] = data_in ;

//$display ("O_ADDR=%X, O_DATA=%x",addr, data_in);

end

end

endmodule

 

 

module x_ram (addr, data_wire,clk,we);

input [4:0] addr ;

inout [23:0] data_wire ;

input we ;

input clk ;

reg [23:0] mem[31:0] ;

wire [23:0] data_in, data_out ;

 

assign data_in = data_wire ;

assign data_out = mem[addr];

 

assign data_wire = (~we) ? data_out: 24'hZZZZZZ;

always @(posedge clk)

begin

if(we ) begin

mem[addr] = data_in ;

//$display ("X_ADDR=%X, X_DATA=%x",addr, data_in);

end

end

endmodule