module comb_heir_top (clk,
reset,
mode,
idct_done,
fir_sample,
fir_result,
fir_start,
fir_done,
start,
din,
params,
dout,
ready,
iir_done,
iir_start,
start_for_idct,
done,
idct_start,
idct_din,
idct_dout,
c_addr,
c_data,
x_addr,
x_data,
x_we,
t_addr,
t_data,
t_we,
o_addr,
o_data,
o_we);
input clk, reset,start;
input [1:0] mode;
input [7:0] fir_sample;
output [9:0] fir_result;
output fir_done,
idct_done,
iir_done;
output fir_start;
 
//for iir
input [7:0] din;
output iir_start;
input [15:0] params;
output [7:0] dout;
wire [7:0] dout;
output ready;
//for idct
input start_for_idct;
input [11:0] idct_din;
output done;
output [8:0] idct_dout;
output idct_start;
// C COEFFICENTS ROM INTERFACE (26x32)
input [25:0] c_data ;
output [4:0] c_addr ;
 
// X (D_IN) RAM INTERFACE (24x32)
inout [23:0] x_data ;
output [4:0] x_addr ;
output x_we ;
// TRANSPOSE RAM INTERFACE (32x32)
inout [31:0] t_data ;
output [4:0] t_addr ;
output t_we ;
// OUTPUT RAM INTERFACE (9x64)
inout [8:0] o_data ;
output [5:0] o_addr ;
output o_we ;
 
wire idct_done,iir_done,fir_done,
fir_start,iir_start,idct_start;
 
 
 
 
comb_contr contr
(.clk(clk),
.reset(reset),
.mode(mode),
.idct_done(idct_done),
.idct_start(idct_start),
.fir_start(fir_start),
.fir_done(fir_done),
.iir_done(iir_done),
.iir_start(iir_start));
 
idct idct (.clk(clk),
.reset(reset),
.start_for_idct(start_for_idct),
.done(done),
.idct_start(idct_start),
.idct_done(idct_done),
.idct_din(idct_din),
.idct_dout(idct_dout),
.c_addr(c_addr),
.c_data(c_data),
.x_addr(x_addr),
.x_data(x_data),
.x_we(x_we),
.t_addr(t_addr),
.t_data(t_data),
.t_we(t_we),
.o_addr(o_addr),
.o_data(o_data),
.o_we(o_we)
);
iir iir (.clk(clk),
.reset(reset),
.start(start),
.din(din),
.params(params),
.dout(dout),
.ready(ready),
.iir_start(iir_start),
.iir_done(iir_done));
 
fir2 fir (.clk(clk),
.reset(reset),
.sample(fir_sample),
.result(fir_result),
.fir_start(fir_start),
.fir_done(fir_done));
endmodule