module comb_contr(clk,

reset,

mode,

idct_done,

idct_start,

fir_start,

fir_done,

iir_done,

iir_start);

input clk, reset;

input idct_done,iir_done,fir_done;

input [1:0] mode;

output fir_start,iir_start,idct_start;

 

//for controller

reg [2:0] cont_state;

reg [2:0] cont_nextstate;

reg fir_start,iir_start,idct_start;

 

parameter cont_idle =3'b000,

mode_select =3'b001,

state_idct =3'b010,

state_iir =3'b011,

state_fir =3'b100,

state_finish=3'b101;

 

//CONTROLLER STATE MACHINE

always @(cont_state or fir_done or mode or idct_done or iir_done) begin

case(cont_state )

cont_idle : cont_nextstate <= mode_select;

mode_select : if (mode == 2'b01)

cont_nextstate <= state_idct;

else

if (mode == 2'b10)

cont_nextstate <= state_iir;

else

if (mode == 2'b11)

cont_nextstate <= state_fir;

else

cont_nextstate <= mode_select;

state_idct : if (idct_done)

cont_nextstate <= state_finish;

else

cont_nextstate <= state_idct;

state_iir : if (iir_done)

cont_nextstate <= state_finish;

else

cont_nextstate <= state_iir;

state_fir : if (fir_done)

cont_nextstate <= state_finish;

else

cont_nextstate <= state_fir;

state_finish : cont_nextstate <= cont_idle;

default : cont_nextstate <= cont_idle;

endcase

end

 

always @(posedge clk) begin

if (reset)

cont_state <= cont_idle;

else

cont_state <= cont_nextstate;

end

 

always @(posedge clk) begin

if (reset || (cont_state == state_finish))

idct_start <= 1'b0;

else

if (cont_state == state_idct)

idct_start <= 1'b1;

else

idct_start <= idct_start;

end

 

always @(posedge clk) begin

if (reset || (cont_state == state_finish))

iir_start <= 1'b0;

else

if (cont_state == state_iir)

iir_start <= 1'b1;

else

iir_start <= iir_start;

end

 

always @(posedge clk) begin

if (reset || (cont_state == state_finish))

fir_start <= 1'b0;

else

if (cont_state == state_fir)

fir_start <= 1'b1;

else

fir_start <= fir_start;

end

 

 

endmodule