module alu_test;

 

wire [15:0] alu_out;

reg [15:0] data, accum;

reg [7:0] arr[5:0];

reg [7:0] opcode;

reg start_clk;

integer i;

 

alu alu1 ( alu_out,carry,opcode,data,accum,clk);

 

`define ADC 8'h13

`define DIV 8'hf6

`define SBB 8'h1C

`define OR 8'h0B

`define SAL 8'h34

`define SAR 8'h35

`define period 20

`define prop_delay 4

 

initial

$timeformat(-9,1, "ns", 9);

 

 

nand #(`period/2) (clk,clk,start_clk);

initial

begin

arr[0] = 8'h13;

arr[1] = 8'hf6;

arr[2] = 8'h1c;

arr[3] = 8'h0b;

arr[4] = 8'h34;

arr[5] = 8'h35;

end

initial

begin

start_clk = 0;

#(`period/2) start_clk =1;

end

 

/**********************

Apply stimulus

 

************************/

 

initial

begin

accum= 16'hDF;

data = 16'h0f;

for(i=0;i<=5;i=i+1)

begin

@ (posedge clk)

begin

accum = accum+1;

#(`period/2 -1) opcode = arr[i];

end

@ (negedge clk)

# `prop_delay check_outputs;

end

//Verify for unknown opcode

@ (posedge clk)

#(`period/2 -1) opcode = 8'h55;

@ (negedge clk)

# `prop_delay check_outputs;

 

repeat(2) @(posedge clk)

$stop;

end

/*

initial

// allow time for interactive debuging

#1000 $finish;

*/

task check_outputs;

begin

casez(opcode)

`ADC : begin

#1;

$display("ADD operation ;","%b %d %d | %d ",opcode,data,accum,alu_out);

end

 

`DIV : begin

#1;

$display("DIV operation ;","%b %d %d | %d %d ",opcode,data,accum,alu_out[15:8],alu_out[7:0]);

end

 

`SBB : begin

#1;

$display("SBB operation ;","%b %d %d | %d ",opcode,data,accum,alu_out);

end

 

`OR : begin

#1;

$display("OR operation ;","%b %d %d | %d ",opcode,data,accum,alu_out);

end

 

`SAL : begin

#1;

$display("SAL operation ;","%b %d %d | %d ",opcode,data,accum,alu_out);

end

 

`SAR : begin

#1;

$display("SAR operation ;","%b %d %d | %d ",opcode,data,accum,alu_out);

end

 

default: $display("Unknown operation ","%b %d %d | %d ",opcode,data,accum,alu_out);

endcase

end

endtask

endmodule